AMS Design Verification Intern — Hands-on Growth in Milan

Analog Devices, Inc.; Lombardia; Hybrid; EUR 7,800 - 12,000; Full time

Benefits offered by this job

Master thesis opportunity

Mentoring and career development

Job summary

Analog Devices, Inc. in Milan, Italy, offers an AMS Design Verification Internship focused on analog/mixed-signal verification. You will model blocks, run AMS simulations, and contribute to verification environments under guidance from experienced engineers.

This internship provides hands-on learning with Verilog-AMS/SystemVerilog and UVM, and may include a Master Thesis opportunity in Analog Mixed Signal Design Verification. Apply to grow in a global tech leader.

Qualifications

• Knowledge of AMS design verification concepts.
• Familiarity with Verilog-AMS and SystemVerilog languages.
• Experience with UVM verification environments is a plus.
• Exposure to analog/mixed-signal verification workflows.
• Interest in internship and potential Master Thesis opportunity.

Responsibilities

• Design specs comprehension and verification plan creation.
• Model analog blocks using Verilog-AMS and SystemVerilog.
• Run AMS simulations and analyze results.
• Verify state machine progression with SystemVerilog assertions.
• Architect and implement metric-driven SystemVerilog/UVM environments.

Skills

AMS design verification

Verilog-AMS

SystemVerilog

UVM

Digital/AMS verification

Tools

Verilog-AMS

SystemVerilog

UVM

Job description

Analog Devices, Inc. in Milan, Italy, offers an AMS Design Verification Internship focused on analog/mixed-signal verification. You will model blocks, run AMS simulations, and contribute to verification environments under guidance from experienced engineers.

This internship provides hands-on learning with Verilog-AMS/SystemVerilog and UVM, and may include a Master Thesis opportunity in Analog Mixed Signal Design Verification. Apply to grow in a global tech leader.