ASIC Mixed-Signal (Analog/Digital) Verification Engineer

Experteer Italy; Pavia; In loco; EUR 50.000 - 90.000; Tempo pieno

Descrizione del lavoro

An innovative firm is seeking a Mixed-Signal Verification Engineer to join their dynamic team in Pavia. This role involves working on cutting-edge technology in the semiconductor industry, focusing on the development and validation of high-speed interface IP. You will collaborate with cross-functional teams to debug and verify analog schematics and engage in verification activities of analog designs. If you are passionate about technology and eager to contribute to groundbreaking projects in a supportive environment, this opportunity is perfect for you.

Competenze

• 5+ years of experience in mixed-signal verification and analog design.
• Master's degree in electronic or micro-electronics engineering required.

Mansioni

• Contribute to the development and validation of complex digital mixed signals.
• Engage in verification activities of analog designs under supervision.

Conoscenze

Analog Design

Digital Design Understanding

Debugging Skills

Problem-Solving Skills

Communication Skills

Teamwork

Formazione

University master's degree in electronic/Micro-electronics engineering

Strumenti

Synopsys Tools

Verilog/VHDL

System Verilog / VMM / UVM

Unix

Perl

TCL Scripting

Spice Simulators

Descrizione del lavoro

ASIC Mixed-Signal (Analog/Digital) Verification Engineer

General Information

Job Title: ASIC Mixed-Signal (Analog/Digital) Verification Engineer

Job ID: 8980

Country: Italy

City: Pavia

Date Posted: 24-Jan-2025

Job Category: Engineering

Job Subcategory: ASIC Digital Design

Hire Type: Employee

Remote Eligible: No

Descriptions & Requirements

Job Description and Requirements

Synopsys, a world leader in the Semiconductor IP industry, is seeking a Mixed Signal Verification Engineer whose responsibilities are:

Main Responsibilities:

1. Work in a Digital and Verification Development team contributing to the development and validation of complex digital mixed signals for high-speed interface IP, having major focus on Analog Schematics.
2. Debug and verify the Analog schematics, support to Analog teams, to faster verify the functionality of Analog Schematics.
3. Understand the IP from a System level, Analog and Digital interactions.
4. Engage in verification activities of analog Designs, under supervision of more experienced personnel, and to exercise judgment to determine appropriate actions to achieve the required specifications.
5. Be able to debug and understand issues related with malfunctions on analog designs.
6. Exposure to mixed signal validations flow. Co-sim.
7. Build productive working relationships, with different teams, cross project.
8. Participate in applicable product/project reviews.
9. Prepare and present reports outlining the outcome of technical projects.

Preferred Technical Experience:

1. Experience in producing high-quality technical documentation is desirable.
2. Experience with analog tools, preferable Synopsys tools.
3. Good understanding of analog design.
4. Experience in Verilog/VHDL.
5. Proficiency in at least one programming language such as Python, C, C++ and MATLAB.
6. Experience in System Verilog /VMM/UVM.
7. Exposure to Unix, Perl and TCL scripting.

Other Qualifications:

1. University master's degree in electronic/Micro-electronics engineering.
2. 5+ years of relevant experience is highly preferred.
3. Knowledge of IC design flows.
4. Analog design knowledge, Digital design understanding.
5. Analog tools and spice simulators understanding.
6. Digital verification tools understanding.
7. Willingness to learn new things.
8. Good team-player with organizational and problem-solving skills.
9. Good English communication skills.

At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things (IOT). These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Synopsys' leading DesignWare IP portfolio is developed by an IP Design Team within Synopsys' Solutions Group. Part of the Team is in Pavia and is staffed with analog and digital IC design engineers, application engineers and test engineers among others. The company's extensive IP portfolio enables next-generation SoC designers to integrate silicon-proven functionality previously available only to large integrated device manufacturers. The IP is licensed to leading semiconductor companies across all major markets, offering high-precision, single-function blocks to complete interface sub-systems.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.