Analog IC Layout Engineer with finFET experience

Chipright; Ferrara; In loco; EUR 50.000 - 80.000; Tempo pieno

Descrizione del lavoro

Chipright is seeking a Senior Analog IC Layout Engineer with extensive finFET experience to join their team. The role involves developing IP for customers while working closely with a team on high-performance analog and mixed-signal circuits, emphasizing collaboration in a dynamic environment.

Competenze

• 7+ years’ experience with Analog / Analog mixed signal IC layout required.
• Knowledge of FinFET process, especially 16nm, 7nm is essential.
• Strong communication and teamwork abilities are important.

Mansioni

• Responsibility for physical design of Analog and Mixed Signal circuits.
• Work on high-performance analog and high-frequency circuits.
• Collaborate with multidisciplinary engineering teams.

Conoscenze

Analog / Analog mixed signal IC layout

FinFET process knowledge

Data Converters layout

Phase Locked Loop (PLL) layout

VerilogA

VerilogAMS

Mixed-signal semiconductor technology

Team collaboration

Excellent communication skills

Fluent in English

Descrizione del lavoro

Analog IC Layout Engineer with finFET experience

Location : N / A

Contract

Senior Analog IC Layout Engineer with finFET experience

Chipright seeks highly motivated and experienced Analog Layout engineers to work in developing and delivering IP to our customers. This is a fantastic opportunity for talented engineers to work within a team of highly experienced engineers with experience in high-speed technology, CMOS, and FinFET.

As an experienced Layout Engineer, you will have first-hand responsibility for the physical design (i.e., the actual implementation) of Analog and Mixed Signal circuits for High-Speed Serializer / Deserializer (SerDes). You will work on high-performance analog and high-frequency circuits in the most scaled CMOS technologies, interact with designers, and drive layout strategies for very complex products.

Requirements

• 7+ years’ minimum experience with Analog / Analog mixed signal IC layout
• Experience / knowledge of the FinFET process, especially 16nm, 7nm
• Layout of Analog IPs such as Data Converters (A / D, D / A), Phase Locked Loop (PLL), Tc / RX reference circuits with emphasis on high-speed applications
• Profound knowledge of hardware description languages (VerilogA, VerilogAMS)
• Collaborate with Applications, Process Technology, CAD, Test, Reliability, Marketing, and Product Engineering
• Excellent understanding of mixed-signal semiconductor circuit technology
• Excellent communication skills and ability to work in a team
• Very good command of English (fluent in spoken and written)

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