Analog IC Layout Engineer with finFET experience

Chipright; Biella; In loco; EUR 50.000 - 80.000; Tempo pieno

Descrizione del lavoro

Chipright is seeking an experienced Senior Analog IC Layout Engineer with FinFET expertise to join their talented team. The role involves physical design responsibilities for high-speed analog circuits and requires strong collaboration skills with multiple engineering functions. Candidates should possess extensive experience in analog layout and knowledge of up-to-date semiconductor technologies, with fluency in English essential for teamwork.

Competenze

• Minimum 7 years’ experience with Analog / Analog mixed signal IC layout.
• Experience with FinFET technology, particularly 16nm and 7nm processes.
• Knowledge of mixed-signal semiconductor circuit technology.

Mansioni

• Responsible for physical design of Analog and Mixed Signal circuits.
• Collaborate with various teams including Applications and Process Technology.
• Drive layout strategies for complex products.

Conoscenze

Analog / Analog mixed signal IC layout

FinFET process knowledge

High-speed applications

Communication skills

Team collaboration

English fluency

Strumenti

VerilogA

VerilogAMS

Descrizione del lavoro

Analog IC Layout Engineer with finFET experience

Location : N / A

Contract

Senior Analog IC Layout Engineer with finFET experience

Chipright seeks highly motivated and experienced Analog Layout engineers to work in developing and delivering IP to our customers. This is a fantastic opportunity for talented engineers to work within a team of highly experienced engineers with experience in high-speed technology, CMOS, and FinFET.

As an experienced Layout Engineer, you will have first-hand responsibility for the physical design (i.e., the actual implementation) of Analog and Mixed Signal circuits for High-Speed Serializer / Deserializer (SerDes). You will work on high-performance analog and high-frequency circuits in the most scaled CMOS technologies, interact with designers, and drive layout strategies for very complex products.

Requirements

• 7+ years’ minimum experience with Analog / Analog mixed signal IC layout
• Experience / knowledge of the FinFET process, especially 16nm, 7nm
• Layout of Analog IPs such as Data Converters (A / D, D / A), Phase Locked Loop (PLL), Tc / RX reference circuits with emphasis on high-speed applications
• Profound knowledge of hardware description languages (VerilogA, VerilogAMS)
• Collaborate with Applications, Process Technology, CAD, Test, Reliability, Marketing, and Product Engineering
• Excellent understanding of mixed-signal semiconductor circuit technology
• Excellent communication skills and ability to work in a team
• Very good command of English (fluent in spoken and written)

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