Analog IC Design Lead - SerDes

JR Italy; Varese; In loco; EUR 80.000 - 120.000; Tempo pieno

Descrizione del lavoro

A fast-growing tech company in Italy is seeking an Analog IC Design Lead to oversee the design strategy for SerDes IP. As part of this senior leadership position, you will guide technical direction, mentor engineers, and ensure the successful release of high-performance products. Candidates must have a strong background in analog and mixed-signal design with over 15 years of experience. This role offers the flexibility of fully remote work.

Competenze

• 15+ years’ industry experience in analog and mixed-signal design.
• Proven leadership in SerDes applications.
• Ability to lead in a fast-paced environment.

Mansioni

• Provide technical leadership for the design of key SerDes IP.
• Oversee development of core analog building blocks.
• Define SerDes architecture in collaboration with teams.
• Establish verification and sign-off strategies.
• Mentor engineering teams, promote best practices.
• Support silicon bring-up and product launch.

Conoscenze

Leadership in analog design

High-speed circuit design

Signal integrity expertise

Power integrity knowledge

Proficiency with EDA tools

Communication skills

Decision-making ability

Formazione

Bachelor’s or Master’s in Electrical Engineering

Descrizione del lavoro

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I am recruiting for an innovative and fast-growing technology company developing next-generation solutions for high-performance data communication. This is a senior leadership role with the flexibility of fully remote working.

As an Analog IC Design Lead, you will take ownership of the full SerDes analog and mixed-signal design strategy, guiding technical direction, mentoring engineers, and ensuring delivery of industry-leading performance. You will shape the architecture, influence design methodologies, and play a pivotal role in the successful release of complex products in advanced CMOS FinFET technologies.

Key Responsibilities

• Provide technical leadership for the design of key SerDes IP
• Oversee and be involved in the development of core analog building blocks
• Define and drive SerDes architecture in collaboration with system architects and other functional teams
• Establish robust verification and sign-off strategies to meet aggressive performance and reliability targets
• Lead and mentor engineering teams, fostering best practices in design, simulation, and layout
• Support silicon bring-up, validation and characterisation, providing direction through to product launch

Requirements

• Bachelor’s or Master’s in Electrical Engineering or related discipline, with 15+ years’ industry experience
• Proven leadership in analog and mixed-signal design for SerDes applications
• Strong expertise in high-speed circuit design, signal integrity, and power integrity
• Proficiency with EDA tools
• Exceptional communication and decision-making skills, with the ability to lead in a fast-paced, collaborative environment

If you are an experienced engineer with a track record in FINFET SerDes design, get in touch with Parm Shergill.