WRD (RTL) Design -Sr Lead

Qualcomm; Hyderabad; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

Qualcomm India Private Limited is seeking a digital design engineer to help develop Wi‑Fi PHY IP. You will work under the lead on RTL coding, micro-architecture, and QA, contributing to the full design life cycle from spec to release.

The role requires strong Verilog/SystemVerilog proficiency, RTL experience, and knowledge of signal processing concepts related to Wi‑Fi standards (802.11 a/b/g/n/ac/ax). Scripting skills (Perl/Tcl) are beneficial.

Qualifications

• B.Tech/ M.Tech in Electronics & Communication with 5–7 years in design and RTL coding.
• Experience with high level synthesis (HLS) is a plus.
• Proficient in Verilog and SystemVerilog; strong RTL QA familiarity.

Responsibilities

• Design, micro-architecture design, RTL coding and validation.
• Collaborate with IP and WiFi PHY teams during requirements and design phases.
• Develop timing constraints for RTL synthesis if required.

Skills

RTL coding

Verilog/SystemVerilog

HLS

Signal processing

WiFi standards

Scripting (Perl/Tcl)

Debugging skills

Education

Bachelors in CSE/EE

Masters in CSE/EE

PhD in CSE/EE

Tools

PLDRC

CDC

CLP

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

BDC WRD (Wi‑Fi) is responsible for developing Qualcomm’s Wi‑Fi chips. We are looking for a digital design engineer, with some signal processing background.

As a design engineer, you will be working with the lead on designing one of the IPs of the WiFi PHY for the upcoming WiFi standard and in the process contribute to the entire life cycle of a design from understanding spec, micro-architecture, RTL coding, RTL QA and making the releases. You will be participating along with the lead in discussions with the WiFi PHY systems team during the requirements phase. It is expected you to have the background and inclination to implement Signal processing module of WiFi in RTL and/or HLS.

Skills & Experience

• MTech/BTech in Electronics & Communication Engineering with 5-7 years in design, micro-architecture & RTL coding.
• Experience with HLS will be a plus.
• Proficient in Verilog, System-Verilog programming languages
• Solid experience with RTL QA flows like PLDRC, CDC, CLP (optional)
• Good to have the working experience either of Implementation or STA flows.
• Knowledge of signal processing concepts/algorithms and Wi‑Fi standards (802.11a/b/g/n/ac/ax) is good to have.
• Good experience in any scripting languages (Perl, Tcl, etc..)
• Strong debugging and problem-solving skills.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
• OR
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
• OR
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Responsibilities

• Design, Micro-architecture design, RTL coding and development and its validation for linting, CDC rules.
• Work with project lead in coming up with the IP micro architecture.
• Work with functional verification team on test-plan development and debug.
• Develop timing constraints, if required, to synthesize the RTL.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• OR
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• OR
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

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