Technical Lead - STA And Synthesis

Quest Global; Hyderabad; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Quest Global in Hyderabad, India, seeks a senior engineer to lead synthesis and static timing analysis across design stages to meet performance, power, and schedule goals. You will own constraints, timing analysis, and closure plans, and collaborate with PnR and clock teams to drive timing convergence.

8–12 years of experience and BE/BTech/MTech in Electronics are required. Expertise with PrimeTime and synthesis tools such as Design Compiler or Fusion Compiler is essential, along with strong

Qualifications

• Expertise with PrimeTime and synthesis tools such as Design Compiler or Fusion Compiler.
• Strong SDC, STA, OCV/AOCV/POCV, and MCMM knowledge.
• Understanding of RTL-to-GDS implementation flows.
• Strong TCL scripting and timing debugging capability.
• Experience in advanced-node timing closure.

Responsibilities

• Own synthesis, constraints, timing analysis, and closure plans.
• Develop and review SDC constraints and timing exceptions.
• Debug setup, hold, transition, capacitance, and constraint issues.
• Drive MCMM timing convergence with PnR and clock teams.
• Lead methodology, automation, reviews, and signoff readiness.

Skills

SDC/STA/MCMM

RTL-to-GDS flow

TCL scripting

Timing closure

Education

BE/BTech/MTech in Electronics

Tools

PrimeTime

Design Compiler

Fusion Compiler

Job description

Job Description:

Job Requirements

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Role Overview

Lead synthesis and static timing analysis strategy, execution, and closure across design stages to meet performance, power, area, and schedule goals.

Key Responsibilities

Own synthesis, constraints, timing analysis, and closure plans

• Develop and review SDC constraints and timing exceptions
• Debug setup, hold, transition, capacitance, and constraint issues
• Drive MCMM timing convergence with PnR and clock teams
• Lead methodology, automation, reviews, and signoff readiness

Required Skills & Expertise

Expertise in PrimeTime and synthesis tools such as Design Compiler or Fusion Compiler

• Strong SDC, STA, OCV/AOCV/POCV, and MCMM knowledge
• Understanding of RTL-to-GDS implementation flows
• Strong TCL scripting and timing debug capability
• Experience in advanced-node timing closure

Preferred Skills

Exposure to Tempus and formal equivalence tools

• Python or Perl scripting is a plus
• Experience leading timing closure across multiple blocks

Experience

8-12 years

Education

BE/BTech/MTech in Electronics or related field

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.