Technical Lead- PD-PV,Full Chip PNR

Quest Global; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

Quest Global Bengaluru is seeking an experienced engineer to lead full-chip netlist integration and readiness, ensuring clean connectivity, hierarchical consistency, and a smooth handoff to implementation and signoff.

The role requires 8–12 years in ASIC/SoC design, strong TCL/Perl/Python scripting, Verilog/SystemVerilog knowledge, and cross‑functional coordination with RTL, synthesis, PnR, STA, DFT, and PV teams. BE/BTech/MTech in Electronics or related field.

Qualifications

• Strong understanding of netlist structure and hierarchical design.
• Experience with synthesis, PnR, STA, and connectivity checks.
• Proficiency in TCL, Perl, or Python scripting.
• Familiarity with Verilog/SystemVerilog and EDA databases.
• Strong debugging and cross-functional coordination skills.

Responsibilities

• Own top-level netlist assembly and integration checks
• Resolve connectivity, hierarchy, naming, and interface issues
• Validate design collateral, constraints, and implementation readiness
• Coordinate with RTL, synthesis, PnR, STA, DFT, and PV teams
• Automate checks and drive issue closure through release

Skills

Netlist structure

Synthesis experience

PnR experience

STA experience

Connectivity checks

TCL scripting

Perl scripting

Python scripting

Verilog/SystemVerilog

EDA databases

Coordination skills

Debugging

Education

BE/BTech/MTech in Electronics

Job description

Job Requirements

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Role Overview

Lead full-chip netlist integration and readiness, ensuring clean connectivity, logical consistency, constraint alignment, and smooth handoff to implementation and signoff.

Key Responsibilities

• Own top-level netlist assembly and integration checks
• Resolve connectivity, hierarchy, naming, and interface issues
• Validate design collateral, constraints, and implementation readiness
• Coordinate with RTL, synthesis, PnR, STA, DFT, and PV teams
• Automate checks and drive issue closure through release

Required Skills & Expertise

Strong understanding of netlist structure and hierarchical design

• Experience with synthesis, PnR, STA, and connectivity checks
• Proficiency in TCL, Perl, or Python scripting
• Familiarity with Verilog/SystemVerilog and EDA databases
• Strong debugging and cross-functional coordination skills

Preferred Skills

Full-chip integration experience on large SoCs

• Exposure to formal or equivalence checking
• Knowledge of DFT and low-power intent is a plus

Experience

8-12 years

Education

BE/BTech/MTech in Electronics or related field

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the world's hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.