Technical Lead – LINT, CDC & RDC Verification

NXP Semiconductors; Dadri; Hybride; INR 2 000 000 - 3 000 000; Plein temps

Résumé du poste

NXP Semiconductors NV seeks a senior Verification Lead for LINT, CDC, and RDC across complex SoCs/IPs. You will define enterprise-wide signoff methods, drive tool deployment, and guide debugging of intricate verification issues in collaboration with Design, DFT, safety, and CAD teams.

The role requires deep experience with Questa/Lint, CDC, RDC, and SpyGlass suites, and a track record of building scalable verification frameworks and automation.

Qualifications

• 10-15+ years in SoC/IP design verification and signoff.
• Expertise with Siemens Questa CDC/RDC/Lint.
• Experience deploying and qualifying enterprise verification tools.

Responsabilités

• Define and maintain LINT, CDC, and RDC signoff methodologies for IP, Subsystem, and SoC development.
• Drive deployment and qualification of EDA solutions across multiple projects.
• Lead technical reviews and mentor engineers in verification best practices.

Connaissances

LINT verification

CDC verification

RDC verification

Signoff methodology

EDA tool deployment

Automation scripting

Outils

Questa Lint

VC SpyGlass Lint

Questa CDC

VC SpyGlass CDC

SpyGlass RDC

Python/Tcl/Perl automation

Description du poste

Role

Technical Lead – LINT, CDC & RDC Verification

Experience: 10-15+ Years in SoC/IP Design Verification, Signoff Methodology, and EDA Tool Deployment.

Location: Flexible / Hybrid

Job Summary

We are looking for a highly experienced LINT, CDC, and RDC Verification Expert to drive methodology development, qualification, deployment, and signoff across complex SoC and IP programs. The candidate should possess strong expertise in both Siemens Questa CDC/RDC/Lint and Synopsys VC SpyGlass (Lint/CDC/RDC) solutions and be capable of defining enterprise-wide signoff methodologies, debugging complex structural verification issues, and collaborating with design, DFT, safety, and CAD teams.

Key Responsibilities

Technical Leadership

• Define and maintain LINT, CDC, and RDC signoff methodologies for IP, Subsystem, and SoC development.
• Drive deployment and qualification of EDA solutions across multiple projects.
• Establish best practices, waiver management processes, and signoff criteria.
• Lead technical reviews and provide guidance on structural verification issues.

LINT Verification

• Perform RTL quality checks using Questa Lint and VC SpyGlass Lint.
• Analyze and resolve violations related to:Coding styleSynthesis mismatchesFSM issuesDead codeX-propagationClock/reset usageDFT-related checks
• Develop custom rule sets and methodology enhancements.

CDC Verification

• Execute CDC signoff using Questa CDC and VC SpyGlass CDC.
• Analyze:Clock domain crossingsSynchronizer structuresReconvergence issuesData coherency checksHandshake protocol verificationAsynchronous interface validation
• Drive CDC closure and root-cause analysis.

RDC Verification

• Lead Reset Domain Crossing analysis and signoff.
• Debug RDC violations, reset synchronizers, reset sequencing, and metastability risks.
• Collaborate with Design and Functional Safety teams to ensure robust reset architecture.

Methodology & Automation

• Develop Tcl/Python/Perl based automation for verification flows.
• Improve runtime, reporting, and dashboard generation.
• Create reusable verification infrastructure and deployment packages.
• Support CI/CD and regression integration.

Stakeholder Management

• Work closely with Design, DFT, Safety, CAD, and EDA vendors.
• Review tool roadmaps and evaluate new features.
• Mentor engineers and drive technical training programs.

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