Senior/Principal verification Engineer

NXP Semiconductors; Hyderabad; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

NXP Semiconductors in Hyderabad, India is seeking an experienced Verification Lead to define verification strategies and drive end-to-end SoC verification across blocks, subsystems, and full platforms. You will architect scalable UVM-based environments, develop reusable UVCs, and mentor teams on best practices.

The role requires hands-on expertise in SystemVerilog, UVM, and formal assertion techniques, with a track record of delivering sign-off-ready verification across complex IPs.

Qualifications

• Experience in SystemVerilog/UVM-based verification.
• Ability to develop test plans and sign-off criteria.
• Experience debugging across IPs and subsystems.

Responsibilities

• Define comprehensive verification strategies and plans based on architecture and design specs.
• Develop and execute block-, subsystem-, and SoC-level verification environments.
• Drive verification closure through functional, code, assertion, and toggle coverage metrics.
• Create test plans, verification testcases, and sign-off criteria.
• Architect and develop scalable SystemVerilog/UVM-based verification environments.
• Design reusable verification components (UVCs), scoreboards, checkers, monitors, and reference models.
• Develop constrained-random, directed, and scenario-based tests.
• Integrate third-party VIPs and custom verification IPs.
• Develop SystemVerilog Assertions for protocol and functional checking.
• Collaborate with formal verification teams for property development and closure.
• Analyze simulation failures and identify RTL, testbench, or architectural issues.
• Lead complex debug activities across multiple IPs and subsystems.
• Define and track functional coverage models.
• Drive functional, code, assertion, and cross-coverage closure.
• Review verification metrics and provide sign-off recommendations.
• Ensure compliance with overall project verification and quality goals.
• Lead end-to-end verification of large SoCs including: interconnect, cache coherency, memory subsystem, boot and reset validation, low-power verification, performance and stress testing.
• Provide technical leadership to verification teams.
• Mentor junior and senior engineers on UVM, verification methodologies, and debug techniques.
• Participate in hiring, technical interviews, and project planning.
• Drive best practices and verification process improvements.

Skills

SystemVerilog

UVM

verification environments

debug techniques

leadership

Tools

UVCs

scoreboards

verification IPs

reference models

Job description

Verification Planning & Execution

• Define comprehensive verification strategies and verification plans based on architecture and design specifications.
• Develop and execute block-level, subsystem-level, and SoC-level verification environments.
• Drive verification closure through functional, code, assertion, and toggle coverage metrics.
• Create test plans, verification testcases, and sign-off criteria.

Testbench Development

• Architect and develop scalable SystemVerilog/UVM-based verification environments.
• Design reusable Verification Components (UVCs), scoreboards, checkers, monitors, and reference models.
• Develop constrained-random, directed, and scenario-based tests.
• Integrate third-party VIPs and custom verification IPs.

Assertion & Formal Verification

• Develop SystemVerilog Assertions (SVA) for protocol and functional checking.
• Utilize assertion-based verification techniques to improve bug detection efficiency.
• Collaborate with formal verification teams for property development and closure.

Debug & Root Cause Analysis

• Analyze simulation failures and identify RTL, testbench, or architectural issues.
• Work closely with design and architecture teams to resolve functional and performance-related bugs.
• Lead complex debug activities across multiple IPs and subsystems.

Coverage & Sign-Off

• Define and track functional coverage models.
• Drive functional, code, assertion, and cross-coverage closure.
• Review verification metrics and provide sign-off recommendations.
• Ensure compliance with overall project verification and quality goals.

SoC Verification

• Lead end-to-end verification of large SoCs including:
  • Interconnect and fabric verification
  • Cache coherency verification
  • Memory subsystem verification
  • Boot and reset validation
  • Low-power verification
  • Performance and stress testing

Leadership & Mentoring

• Provide technical leadership to verification teams.
• Mentor junior and senior engineers on UVM, verification methodologies, and debug techniques.
• Participate in hiring, technical interviews, and project planning.
• Drive best practices and verification process improvements.

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