STA lead/engineers

ACL Digital; Bengaluru; On-site; INR 1,200,000 - 1,700,000; Full time

Job summary

ACL Digital is hiring for Static Timing Analysis roles in Bengaluru, with openings across Bangalore, Hyderabad, and Chennai. The team seeks hands-on VLSI professionals to join its timing closure group and drive signoff through all stages of SoC development.

Key requirements include a B.E./B.Tech or M.E./M.Tech in ECE/Electrical/VLSI/Microelectronics and hands-on experience with PrimeTime, Tempus, QRC, and other STA tools. Proven track record on finFET nodes is expected.

Qualifications

• Hands-on experience with STA and signoff tools for complex SoCs.
• Proven track record on advanced finFET nodes.
• Experience driving timing signoff from synthesis through PnR to tapeout.

Responsibilities

• Full-Chip Timing Closure: Own and drive timing signoff for complex SoCs across all modes and corners from synthesis through PnR to tapeout.
• STA & Analysis: Execute setup, hold, recovery/removal, clock gating, and async path analysis.
• Advanced Effects: Resolve issues related to cross-talk, noise, OCV/AOCV/POCV, derates, and variation effects in 7nm / 5nm / 3nm nodes.
• ECO Closure: Lead timing ECO strategies for minimal PPA impact.
• Methodology & Quality: Drive implementation vs. signoff correlation, enforce best practices, and mentor junior/mid-level STA engineers.

Skills

Timing closure

STA analysis

Mentoring

PPA awareness

Education

B.E./B.Tech or M.E./M.Tech in ECE/Electrical/VLSI/Microelectronics

Tools

PrimeTime

Tempus

QRC

Job description

WE ARE HIRING | Static Timing Analysis (STA) Roles at ACL Digital!

Are you passionate about tackling timing challenges on complex, advanced-node SoCs? ACL Digital is expanding its VLSI team across Bangalore, Hyderabad, and Chennai!

We are looking for hands-on, high-performing VLSI professionals to join our timing closure team:

Open Roles:

Locations: Bangalore / Hyderabad / Chennai

Key Responsibilities (Lead Role):

• Full-Chip Timing Closure: Own and drive timing signoff for complex SoCs across all modes and corners from synthesis through PnR to tapeout.
• STA & Analysis: Execute setup, hold, recovery/removal, clock gating, and async path analysis.
• Advanced Effects: Resolve issues related to cross-talk, noise, OCV/AOCV/POCV, derates, and variation effects in 7nm / 5nm / 3nm nodes.
• ECO Closure: Lead timing ECO strategies for minimal PPA impact.
• Methodology & Quality: Drive implementation vs. signoff correlation, enforce best practices, and mentor junior/mid-level STA engineers.

Key Requirements:

• B.E/B.Tech/M.E/M.Tech in ECE / Electrical / VLSI / Microelectronics.
• Hands-on expertise with industry-standard STA and signoff tools (PrimeTime, Tempus, QRC, etc.).
• Proven track record on advanced finFET nodes.