Static Time Analysis Engineer

Capgemini Engineering; Bengaluru; In loco; INR 1.000.000 - 1.500.000; Tempo pieno

Descrizione del lavoro

A leading engineering services company in Bengaluru is seeking an experienced Analysis Engineer. The role involves performing timing analysis, developing constraints, and integrating STA tools into the design flow. The ideal candidate will possess deep technical knowledge of STA methodologies and tools. This full-time position offers opportunities for leadership and teamwork across multiple engineering functions.

Competenze

• In-depth understanding of STA concepts and methodologies.
• Strong analytical abilities to tackle complex timing issues.
• Experience in timing closure for Full-Chip/Sub-system.

Mansioni

• Perform setup, hold, and skew analysis across various levels.
• Define and validate timing constraints for Full-Chip.
• Integrate STA into the overall design flow for efficiency.

Conoscenze

Deep Technical Knowledge

Problem-Solving Skills

Communication Skills

Leadership and Mentoring

Strumenti

Synopsys PrimeTime

Cadence Tempus

ModelSim

Descrizione del lavoro

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Overview

Talent Acquisition/ Sourcing / Recruitment in Capgemini Engineering

Responsibilities

• Timing Analysis & Closure
• Perform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels.
• Achieve timing closure by resolving violations and optimizing paths.
• Constraint Development
• Define and validate timing constraints (clocks, I/O delays, false/multi-cycle paths).
• Integrate constraints from multiple IPs for hierarchical STA.
• Tool Usage & Flow Integration
• Use STA tools like Synopsys PrimeTime, Cadence Tempus, or equivalent.
• Integrate STA into the overall design flow and automate processes for efficiency.

Job Description

• Provide expert guidance on STA methodologies, including setup and hold time analysis, clock domain crossing, and multi-cycle paths for Full Chip, Sub-system and complex IP timing closure.
• Define and implement timing constraints from scratch such as clock definitions, input/output delays, and path constraints for Full-Chip, Sub-system to ensure accurate timing analysis.
• Able to integrate the existing timing constraints from various IP for Full-Chip/Sub-system timing analysis.
• Deep knowledge of STA tools (such as Synopsys PrimeTime, Cadence Tempus, or Mentor Graphics' ModelSim) including their capabilities, limitations, and best practices.
• Guide the integration of STA tools into the overall design flow, ensuring compatibility and optimal performance.
• Oversee the process of achieving timing closure, addressing any timing violations and guiding optimizations to meet performance goals.

Primary Skills

• Deep Technical Knowledge
• In-depth understanding of STA concepts, EDA tools, and methodologies.
• Experience in timing constraints development, timing closure for Full-Chip/Sub-system to meet the design performance.
• Problem-Solving Skills: Strong analytical and problem-solving abilities to tackle complex timing issues.
• Communication Skills: Ability to communicate complex technical concepts effectively to various stakeholders.
• Leadership and Mentoring
• Experience in leading teams and mentoring less experienced engineers in STA practices

Secondary skills

• Design flow management
• Able to improve the execution efficiency through flow automation and other value adds
• Cross functional co-ordination
• Work closely with other teams, such as RTL design, Physical design, design, verification, and manufacturing, to ensure seamless timing closure of physical design.

Seniority

• Associate

Employment type

• Full-time

Job function

• Consulting, Engineering, and Other
• Industries: Engineering Services, IT Services and IT Consulting, and Business Consulting and Services

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