Senior Digital Verification Engineer

Synopsys India Pvt Ltd; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Synopsys India Pvt Ltd in Bengaluru is seeking a Staff Digital Verification Engineer with 4+ years of hands‑on verification experience to build and evolve SystemVerilog/UVM environments for DesignWare IP cores and define comprehensive test plans for DDR/LPDDR interfaces.

You will own verification closure for critical DDR PHY blocks, collaborate with RTL and architecture teams, and drive regression and coverage metrics to sign‑off on releases.

Qualifications

• Bachelor's or Master's in Electrical Engineering or Electronics and Communication Engineering with 4+ years of hands-on verification experience.

Responsibilities

• Build and evolve SystemVerilog/UVM verification environments for DesignWare synthesizable IP cores, ensuring they scale across multiple product generations and configurations.
• Define comprehensive test plans that cover corner cases, protocol compliance, and system-level interactions for serial interface protocols and memory controllers, including DDR and LPDDR where applicable.
• Write and debug complex testbenches, checkers, and assertions that catch real bugs in critical PHY blocks and interface logic.
• Develop software requirements for the PHY that scale across various configurations and use cases.
• Own verification closure for multiple critical blocks within DDR PHYs, including functional coverage, code coverage, and formal signoff.
• Collaborate with RTL designers, digital architects, and circuit teams to align verification scope with design intent and surface issues early in the design cycle.

Skills

SystemVerilog

UVM

Testbenches

Assertions

Coverage Metrics

Education

Electrical/EC Engineering degree

Tools

AI-assisted verification tools

Job description

Staff Digital Verification Engineer

General Information

Job Title Staff Digital Verification Engineer

Job ID 18900

Country India

City Bengaluru

Date Posted 21-Sep-2026

Job Category Engineering

Job Subcategory ASIC Digital Design

Hire Type Employee

Remote Eligible No

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

What You'll Be Doing

• Build and evolve SystemVerilog/UVM verification environments for DesignWare synthesizable IP cores, ensuring they scale across multiple product generations and configurations
• Define comprehensive test plans that cover corner cases, protocol compliance, and system-level interactions for serial interface protocols and memory controllers, including DDR and LPDDR where applicable
• Write and debug complex testbenches, checkers, and assertions that catch real bugs in critical PHY blocks and interface logic
• Develop software requirements for the PHY that scale across various configurations and use cases
• Own verification closure for multiple critical blocks within DDR PHYs, including functional coverage, code coverage, and formal signoff
• Collaborate directly with RTL designers, digital architects, and circuit teams to align verification scope with design intent and surface issues early in the design cycle
• Manage regression infrastructure and work with the infra team to optimize verification cycles, debug failures, and keep the environment reliable

The Impact You Will Have

• Your verification environments will catch critical bugs before tapeout, directly affecting the quality and time-to-market of DesignWare IP used across the semiconductor industry
• The test plans you define and review will set the verification standard for the team, ensuring consistent coverage and reducing escapes
• Your coverage-driven approach will surface gaps that others miss, leading to more robust IP and fewer silicon respins
• The assertions and checkers you write will become reusable verification IP, accelerating future projects and raising the quality bar
• Your collaboration with RTL and architecture teams will shape design decisions early, making designs easier to verify and more reliable in the field
• The regression strategies you implement will directly improve team productivity and reduce verification cycle time
• Your ownership of critical PHY blocks will ensure that high-stakes features meet functional and performance requirements on schedule

What You'll Need

• Bachelor's or Master's in Electrical Engineering or Electronics and Communication Engineering with 4+ years of hands-on verification experience
• Proven track record leading verification teams through IP project delivery, including planning, execution, and signoff
• Strong experience developing SystemVerilog/UVM testbenches from scratch and evolving them as designs grow in complexity
• Deep expertise writing test plans, implementing checkers, and building assertions that catch real bugs, not just toggle coverage
• Proficiency extracting and interpreting functional coverage and code coverage metrics, and using those insights to drive verification closure
• Experience verifying serial interface protocols and working through IP design and verification processes, knowledge of DDR or LPDDR protocols is a strong plus
• Demonstrated ability to own end-to-end verification deliverables, including metric closure and formal review signoff, experience with AI-assisted verification tools is a plus

Who You Are

• You can walk into a coverage review, spot the gap in the test plan, and articulate exactly what scenario is missing and why it matters
• You write assertions that encode real design intent, not just the obvious cases, and you know the difference between a checker that catches bugs and one that just makes noise
• You are comfortable leading technical discussions with RTL designers and architects, pushing back when verification scope is unclear or the interface is going to create downstream pain
• You manage multiple verification efforts in parallel without losing track of what is at risk, what is on schedule, and what needs attention today
• You debug with purpose, you do not just stare at waveforms hoping for insight, you form hypotheses, test them, and move systematically toward root cause
• You treat verification infrastructure as a product, you care about regression efficiency, debug turnaround time, and whether your environment is actually usable by the rest of the team

The Team You'll Be Part Of Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Experience Level Senior Level