Sr Staff ASIC Verification Engineer

Synopsys Inc; Bengaluru; On-site; INR 3,500,000 - 5,200,000; Full time

Job summary

Synopsys Inc. is seeking an experienced verification leader to own end-to-end verification for major IP blocks and cross-IP methodologies.

You will shape strategy, architecture, and sign-off criteria for complex protocols like Ethernet and USB, while guiding multiple teams to deliver high-quality silicon-ready IP. You will apply AI-assisted techniques for efficient debugging, regression analytics, test generation, and coverage closure, and you will mentor engineers across design, architecture,

Qualifications

• 8+ years of IP or SoC verification experience with ownership of complex verification
• Proven ability to lead verification teams through strategy and execution
• Hands-on expertise in UVM, VMM, or OVM methodologies and verification environments

Responsibilities

• Own verification for a major IP block, subsystem, or cross-IP methodology from architecture through signoff
• Define verification strategy, planning, architecture, and signoff criteria for Ethernet/USB like protocols
• Lead technical execution across verification teams by setting objectives, tracking milestones, and driving coverage and quality closure
• Apply AI-assisted verification techniques to debugging, regression analytics, test generation, and coverage closure
• Build and drive reusable verification infrastructure, UVM environments, and methodology improvements across IP domains

Skills

IP verification

Ownership

UVM/OVM/VMM

SystemVerilog

AI-assisted verification

Education

B.E./B.Tech in EE/EC

Tools

VCS

SV Debug tools

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years verifying complex IP and you know the difference between a verification plan that looks complete on paper and one that actually catches the corner case that would have escaped to silicon. Ownership is not a buzzword for you, it is how you work. When you take on an IP or subsystem, you see the entire arc from architecture through signoff, and you know which risks matter in week two versus week twenty. You do not wait for someone to tell you the methodology is broken. You see it, you fix it, and you bring the rest of the team along. Leading without a title comes naturally because people trust your judgment and your ability to translate a messy verification problem into a plan that actually closes coverage. You have debugged enough failing tests to know when to dig deeper and when to step back and rethink the approach. Mentorship matters to you, not as a checkbox but because you remember the engineer who showed you how to think about verification strategy, and you want to be that person for someone else.

What You'll Be Doing

• Own verification for a major IP block, subsystem, or cross-IP methodology from architecture definition through final signoff and customer delivery
• Define verification strategy, planning, architecture, and signoff criteria for complex IP projects including Ethernet, USB, and similar industry-standard protocols
• Lead technical execution across verification teams by setting objectives, tracking milestones, managing risk, and driving coverage and quality closure
• Apply AI-assisted verification techniques to intelligent debug, regression analytics, test generation, and coverage closure to measurably reduce cycle time and improve defect detection
• Build and drive reusable verification infrastructure, UVM environments, and methodology improvements that scale across multiple IP domains and projects
• Mentor verification engineers on test planning, debug strategies, coverage analysis, and verification best practices while fostering technical growth across the team
• Collaborate with design, architecture, firmware, and quality teams to align verification deliverables with project goals and ensure high-quality IP releases

The Impact You Will Have

• Deliver thoroughly verified, customer-ready DesignWare IP that reduces integration risk and increases confidence for silicon teams building next-generation products
• Drive measurable improvements in verification efficiency including faster coverage closure, shorter regression cycles, reduced debug time, and fewer escaped defects
• Advance verification methodologies and reusable infrastructure that improve execution quality and delivery predictability across IP projects
• Strengthen the technical capability of the verification organization by mentoring engineers and establishing best practices that scale
• Reduce project risk by identifying verification gaps early, optimizing processes, and ensuring robust signoff criteria are met before release
• Enable Synopsys to maintain leadership in IP quality and reliability during the era of pervasive intelligence and AI-powered silicon design
• Contribute to the success of customers who depend on Synopsys IP to power critical functions in their chips, from data centers to automotive to mobile devices

What You'll Need

• BS or BE in Electrical or Electronics Engineering with 8+ years of IP or SoC verification experience, or MS with 6+ years
• Demonstrated ownership of verification for complex IP blocks, subsystems, or cross-project methodologies with a track record of delivering measurable quality and coverage results
• Proven ability to lead verification teams and projects through technical influence, expertise, and collaboration rather than formal management authority
• Deep hands-on expertise in UVM, VMM, or OVM methodologies applied to real verification environments at unit and system levels
• Strong proficiency in SystemVerilog, industry-standard simulators like VCS, and associated debug tools used in complex IP verification workflows
• Practical experience applying AI-assisted methods to debug, regression optimization, test generation, or verification closure activities
• Experience with DesignWare IP or similar synthesizable IP verification, and familiarity with protocols such as Ethernet, USB, or PCI Express is a strong plus

Who You Are

• You lead through expertise and influence, not authority, and engineers follow your technical direction because they trust your judgment and your ability to solve hard problems
• You own complex verification areas end to end, from defining strategy and architecture through executing the plan, managing risks, and driving signoff without needing constant oversight
• You can explain a verification bottleneck, a coverage gap, or a project risk to a design lead or program manager in two sentences without losing the technical nuance that matters
• You combine strategic thinking with attention to detail, knowing when to zoom out to assess methodology and when to dive into a waveform to find the root cause
• You mentor engineers by sharing not just what to do but how to think about verification problems, coverage strategies, and trade-offs in a way that builds their capability over time
• You adapt quickly in evolving project environments, shifting priorities, and ambiguous requirements, and you help the team stay focused on what actually moves the needle toward delivery

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.