Staff Design Verification Infrastructure Engineer - VIPs and Testbench

SiFive India Private Limited; Bengaluru; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

SiFive India Private Limited is seeking an experienced Design Verification Engineer to develop and maintain Component Verification Platforms (EVPs) and related testbench artifacts. This role involves architecting and developing the Verification Platform and educating teams on best practices.

The ideal candidate will have over 7 years of design verification experience, strong proficiency in SystemVerilog and UVM, and knowledge of Scala and Chisel.

Qualifications

• Typically 7+ years of experience in design verification.
• Experience designing and verifying VIPs and other testbench components.
• Understanding of modern software engineering practices.

Responsibilities

• Architect, develop, and maintain the Verification Platform.
• Develop verification libraries in Scala with Chisel.
• Create VIPs and other testbench components using SystemVerilog and UVM.
• Develop test plans and testbenches for high-quality verification.
• Educate teams on best practices for using the Verification Platform.

Skills

Design Verification experience

SystemVerilog

UVM

Chisel

Scala

Python

Education

BS/MS/PhD in EE/CE/CS or related field

Job description

SiFive develops open-source RISC‑V solutions and is building a high‑performance verification platform for its design teams. SiFive is seeking an experienced Design Verification engineer to develop and maintain Component Verification Platforms (EVPs) and related testbench artifacts.

Responsibilities

• Architect, develop, and maintain the Verification Platform to provide a scalable infrastructure for Design Verification and other validation activities.
• Develop Verification Platform libraries for expressing verification intent in Scala with Chisel, including test harnesses, stimulus, scoreboards, and other generators.
• Create Verification Platform VIPs, AIPs, and other testbench components using SystemVerilog, UVM, and related technologies.
• Develop Verification Platform test plans and testbenches to verify and release testbench components with high quality.
• Educate the Design Verification and other verification and validation teams on best practices and how to achieve them with the Verification Platform.

Requirements

• Design Verification experience with SystemVerilog and UVM.
• Experience designing and verifying VIPs, AIPs, and other testbench components.
• Understanding of modern software engineering practices.
• Typically 7+ years of experience with a BS/MS/PhD in EE/CE/CS or related field.

Desired Skills

• Experience with Chisel, Scala, and/or Python.
• Understanding of EDA tools and flows for Design Verification.
• Familiarity with DevOps practices, build systems, and CI/CD.

Additional Information

This position requires successful background and reference checks, satisfactory proof of right to work in India, and verification that the candidate is authorized for access to export‑controlled technology under applicable export control laws.

EEO Statement

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.