Staff Design Engineer

Aeva; Bengaluru; On-site; INR 2,000,000 - 3,000,000; Full time

Benefits offered by this job

Referral benefits to enhance interview chances

Job summary

A technology company in Bengaluru is seeking a senior engineer for their Digital Design team. The successful candidate will focus on the RTL design and development of components for a 4-D Lidar processing chip. Candidates should have over 10 years of experience in DSP designs, writing SystemVerilog RTL code, and achieving high performance and low power targets. This full-time role emphasizes collaboration with various engineering teams and the implementation of innovative processes.

Qualifications

• 10+ years of experience in DSP design and algorithms.
• Experience writing SystemVerilog RTL code.
• Ability to meet high performance and low power targets.

Responsibilities

• Develop custom sub‑components of the digital signaling pipeline.
• Write micro‑architecture specifications and validate sub‑components.
• Work with engineers to ensure design meets performance targets.

Skills

DSP designs

SystemVerilog RTL

AMBA protocols

Tools

MATLAB

C/C++

Cadence Palladium

Mentor Veloce

Synopsys Zebu

Job description

As a key player on the Digital Design team, you will participate in the RTL design and development of the signal processing path for Aeva’s 4‑D Lidar processing chip. You will be responsible for implementing and/or integrating sub‑components of the design in ASICs and FPGAs.

What you'll be doing:

• Develop custom sub‑components of the digital signaling pipeline like filters, FFTs, control logic, etc.
• Write micro‑architecture specifications, code RTL, test & validate Aeva‑specific sub‑components.
• Implement additional functionality including functional safety and robustness functions.
• Focus on developing efficient, highly reliable, highly available, robust functionality.
• Work with architects, design engineers, verification engineers, and system software teams to ensure that the SOC meets its functional, performance, and power targets.

What you'll have:

• 10+ years of experience in the design of DSP designs, algorithms, and signal processing functionality in ASICs/FPGAs. Ability to achieve high performance and low power targets.
• Experience writing SystemVerilog RTL code.
• Working experience and knowledge in AMBA protocols.
• Desire to learn & implement groundbreaking new processes and methodology for continuous improvement.

Nice to haves:

• MATLAB/NumPy/C/C++.
• Working experience and knowledge in LPDDR, Ethernet, MIPI, and high‑speed SerDes etc.
• Experience in FPGA designs, pre‑silicon validation on emulation platforms such as Cadence Palladium, Mentor Veloce, Synopsys Zebu.
• Post‑silicon bring‑up and validation planning and execution.
• Diagnostics firmware development and validation.

Referral benefits: referrals increase your chances of interviewing at Aeva by 2x.

Seniority level

Not Applicable

Employment type

Full‑time

Job function

Engineering and Information Technology

Industries

Automotive