STA Engineer - EDA/CAD Flow : Software Development Engineer

AMD; Hyderabad; Presencial; INR 1.200.000 - 1.800.000; Jornada completa

Descripción de la vacante

AMD is seeking a dynamic software engineer to join our STA/EDA team. You will contribute to timing analysis, RTL design and P&R flow to deliver high-quality, industry-leading technologies.

The ideal candidate has a strong background in Verilog/VHDL, timing closure concepts, and Linux-based development, with 2–3 years in Digital Design/STA. Join AMD and help move the world forward with innovation.

Formación

• BS or MS in EE or CE with 2-3 years of experience in Digital Design and Static Timing Analysis.
• Strong background in RTL design using Verilog/VHDL.
• Exposure to timing closure concepts and timing analysis.
• Experience with place-and-route concepts and EDA flows.

Responsabilidades

• Create complex designs and debug P&R issues.
• Work to achieve timing closure.
• Contribute to RTL coding and STA concepts within the EDA/CAD flow.

Conocimientos

RTL design

Verilog/VHDL

STA (Static Timing Analysis)

Timing closure concepts

Digital design

Analytical skills

Educación

BS or MS in EE or CE

Herramientas

TCL

Perl

Python

EDA tools

Linux

Descripción del empleo

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

STA Engineer - EDA/CAD Flow : Software Development Engineer

THE ROLE:

We are looking for a dynamic, upbeat software engineer to join our growing team. As a key contributor you will be part of a leading team to drive and enhance AMD’s abilities to deliver the highest quality, industry-leading technologies to market.

THE PERSON:

The ideal candidate should have a strong background in RTL design using Verilog/VHDL and strong exposure to timing closure concepts with foundations in timing analysis & digital design.

KEY RESPONSIBILITIES:

The candidate should have a solid understanding of

• RTL coding styles
• STA and Timing Constraint Concepts
• Place and route algoritms and applications.
• The candidate will be responsible for creating complex designs, debugging P & R issues and will work to achieve timing closure.

PREFERRED EXPERIENCE:

• Scripting language such as TCL, Perl or Python
• EDA tools and flow
• Familiarity with Linux and modern software tools and techniques for development
• Good analytical and problem-solving skills

ACADEMIC CREDENTIALS:

• BS or MS in EE or CE with 2-3 years of experience in Digital Design and Static Timing Analysis

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.