SRAM Memory Design

Samsung; Bengaluru; On-site; INR 1,500,000 - 1,800,000; Full time

Job summary

Samsung Semiconductor India Research (SSIR) in Bengaluru seeks a SRAM Memory Design Engineer to design high-performance, power-efficient SRAM circuits and lead a group of engineers to meet delivery timelines.

You will analyse robustness, review layouts, and drive PPA optimizations while coordinating with multiple teams to ensure SPEC-to-GDS delivery.

Qualifications

• 4–10 years of experience in memory design or related fields.
• Solid understanding of SRAM bit cells, read/standby currents and SNM.
• Familiarity with RC networks and FINFET basics.
• Experience in design from SPEC to GDS delivery.
• Knowledge of layout reviews and robustness improvement.
• Ability to communicate across multiple teams.

Responsibilities

• Design competitive SRAM circuits meeting performance and power specs.
• Lead engineers to deliver SRAM IP within timelines.
• Analyse robustness gaps and implement solutions.
• Review layouts and suggest PPA improvements.
• Oversee design from SPEC to DK delivery.
• Communicate effectively across teams.

Skills

Memory design

SRAM design

Circuit design

PPA trade-offs

Team leadership

Education

B.Tech/BE Electronics

M.Tech/M.E

Job description

Position Summary

Position: SRAM Memory Design Engineer:

Roles and Responsibilities:

• Design highly competitive circuits to meet performance/power specifications requested by customers


• Guide and lead a group of engineers to deliver the SRAM IP in the given timelines


• Analyse circuits and identify potential robustness gaps and find solutions to improve robustness of the design.


• Own the responsibility from SPEC to GDS and DK delivery.


• Review circuits, robustness reports and identify potential robustness issues.


• Review Layouts and suggest improvement areas to achieve competitive PPA


• Understanding of SRAM PPA trade-offs and identify right techniques to meet SPEC


• Must be able to communicate effectively across different teams.

Role and Responsibilities

• Master/Bachelor in electronics


• Working experience in preferably Memory design


• Understanding of RC network and FINFET fundamentals are necessary.


• Custom or Compiler SRAM/ROM development experience


• Fundamentals of process variability and its effect on memory design


• Thorough understanding of SRAM bit cell and its characteristics (Read current, Standby current, data retention, SNM)


• Strong understanding of circuit design fundamentals


• Critical path modelling concept, various type of models ( RC, C, Pai,ladder)


• Good knowledge of semiconductor physics. Like knowledge of finfet function, parasitic etc


• Analysing layout and understanding of LLE effects.

Skills and Qualifications

• Experience - 4 to 10 Years of experience


• Qualifications: B.Tech/B.E/M.Tech/M.E

Disclaimer:

Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law

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