SRAM Memory Design

Samsung Electronics Perú; Bengaluru; On-site; INR 1,400,000 - 2,100,000; Full time

Job summary

Samsung Semiconductor India Research (SSIR) in Bengaluru seeks a SRAM Memory Design Engineer to drive circuit design, validation and SRAM IP delivery from SPEC to GDS. The role includes leading a team, optimizing PPA, and ensuring robustness on tight timelines.

The candidate should hold a Master or Bachelor in electronics with memory design experience and a deep understanding of FINFET, RC networks, and SRAM bit cell behavior, plus strong cross-team communication.

Qualifications

• Master/Bachelor in electronics required.
• Working experience in preferably Memory design.
• Understanding of RC network and FINFET fundamentals.
• Custom or Compiler SRAM/ROM development experience.
• Fundamentals of process variability and its effect on memory design.
• Thorough understanding of SRAM bit cell and its characteristics (Read current, Standby current, data retention, SNM).
• Strong understanding of circuit design fundamentals.
• Critical path modelling concept and RC, C, Pai, ladder models.

Responsibilities

• Design circuits to meet performance/power specs.
• Guide and lead engineers to deliver SRAM IP on time.
• Analyze circuits to identify robustness gaps and fix issues.
• Own the SPEC to GDS delivery lifecycle.
• Review robustness reports and layout for improvements.
• Communicate effectively across teams.

Skills

SRAM design

Memory design

RC network basics

FINFET fundamentals

Circuit design fundamentals

PPA trade-offs

Layout/LLE analysis

Education

Master/Bachelor in electronics

Memory design preferred

Tools

Custom SRAM/Compiler SRAM/ROM development

Job description

Position Summary Position: SRAM Memory Design Engineer:

Roles and Responsibilities:

• Design highly competitive circuits to meet performance/power specifications requested by customers
• Guide and lead a group of engineers to deliver the SRAM IP in the given timelines
• Analyse circuits and identify potential robustness gaps and find solutions to improve robustness of the design.
• Own the responsibility from SPEC to GDS and DK delivery.
• Review circuits, robustness reports and identify potential robustness issues.
• Review Layouts and suggest improvement areas to achieve competitive PPA
• Understanding of SRAM PPA trade-offs and identify right techniques to meet SPEC
• Must be able to communicate effectively across different teams.

Role and Responsibilities Skills & Experience:

• Master/Bachelor in electronics
• Working experience in preferably Memory design
• Understanding of RC network and FINFET fundamentals are necessary.
• Custom or Compiler SRAM/ROM development experience
• Fundamentals of process variability and its effect on memory design
• Thorough understanding of SRAM bit cell and its characteristics (Read current, Standby current, data retention, SNM)
• Strong understanding of circuit design fundamentals
• Critical path modelling concept, various type of models ( RC, C, Pai,ladder)
• Good knowledge of semiconductor physics. Like knowledge of finfet function, parasitic etc
• Analysing layout and understanding of LLE effects.

Experience – 4 to 10 Years of experience Qualifications: B.Tech/B.E/M.Tech/M.E

Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law *

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