SRAM Memory Design

Samsung Electronics; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Samsung Semiconductor India Research (SSIR) Bangalore is seeking a SRAM Memory Design Engineer to drive high-performance memory circuits from concept to GDS delivery.

You will lead a team, analyze circuit robustness, and ensure SRAM IP meets customer specifications while coordinating with design, layout, and reliability groups.

Qualifications

• 4–10 years of experience in memory design.
• Experience in SRAM/ROM development.
• Understanding RC networks and FINFET fundamentals.
• Knowledge of process variability effects on memory design.
• SRAM bit cell concepts: read/standby/data retention/SNM.
• Strong circuit design fundamentals.
• Critical path modelling and RC/C/Pai/ladders concepts.
• Solid understanding of semiconductor physics and parasitics.
• Layout analysis and LLE effects awareness.

Responsibilities

• Design SRAM memory circuits to meet performance and power specs.
• Lead engineers to deliver SRAM IP on schedule.
• Analyze circuits for robustness and propose improvements.
• Own SPEC to GDS and DK delivery.
• Review layouts and robustness reports for issues.
• Communicate across teams to coordinate development.

Skills

SRAM design

Circuit design fundamentals

PPA trade-offs

Layout review

RC network

FINFET fundamentals

memory design experience

data retention (SNM)

Education

B.Tech/B.E./M.Tech/M.E.

Tools

Layout awareness

Job description

Position Summary

Position: SRAM Memory Design Engineer:

Roles and Responsibilities:

• Design highly competitive circuits to meet performance/power specifications requested by customers
• Guide and lead a group of engineers to deliver the SRAM IP in the given timelines
• Analyse circuits and identify potential robustness gaps and find solutions to improve robustness of the design.
• Own the responsibility from SPEC to GDS and DK delivery.
• Review circuits, robustness reports and identify potential robustness issues.
• Review Layouts and suggest improvement areas to achieve competitive PPA
• Understanding of SRAM PPA trade-offs and identify right techniques to meet SPEC
• Must be able to communicate effectively across different teams.

Role and Responsibilities

Skills & Experience:

• Master/Bachelor in electronics
• Working experience in preferably Memory design
• Understanding of RC network and FINFET fundamentals are necessary.
• Custom or Compiler SRAM/ROM development experience
• Fundamentals of process variability and its effect on memory design
• Thorough understanding of SRAM bit cell and its characteristics (Read current, Standby current, data retention, SNM)
• Strong understanding of circuit design fundamentals
• Critical path modelling concept, various type of models ( RC, C, Pai,ladder)
• Good knowledge of semiconductor physics. Like knowledge of finfet function, parasitic etc
• Analysing layout and understanding of LLE effects.

Skills and Qualifications

Experience – 4 to 10 Years of experience

Qualifications: B.Tech/B.E/M.Tech/M.E

Disclaimer: Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law

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