Sr. Staff Engineer, Analog/Mixed Signal Modelling and Verification

Ayar Labs; Bengaluru; On-site; INR 400,000 - 700,000; Full time

Job summary

Ayar Labs seeks a Sr. Staff AMS Modelling and Verification Engineer to join its Silicon Engineering team in Bengaluru. You will lead behavioral modelling and verification of high-performance analog/mixed-signal blocks, focusing on PLLs and SerDes across advanced process nodes.

Collaboration with architects and analog designers will define models and drive end-to-end verification. The role requires deep SystemVerilog-RNM and Verilog-AMS expertise, plus experience with Cadence/Synopsys toolchains.

Qualifications

• Associates Degree or equivalent experience required.
• 10+ years hands-on analog/mixed-signal verification with successful tapeouts.
• 5+ years in SerDes verification.
• Deep knowledge of UVM, SystemVerilog-RNM, and Verilog-AMS.
• Advanced proficiency with Cadence and Synopsys AMS toolchains.

Responsibilities

• Develop and sign off on behavioral models for mixed-signal blocks.
• Create test plans for mixed-signal blocks in collaboration with architects.
• Capture critical parameters from schematics and translate into RNM models.
• Integrate AMS IP into full-chip verification environments.

Skills

Analog/mixed-signal modelling

SystemVerilog RNM

Verilog-AMS

UVM

Cadence/Virtuoso

Synopsys VCS

SerDes verification

Python scripting

Education

Associates Degree, or equivalent experience

Tools

Cadence Virtuoso

Spectre

Xcelium

Synopsys VCS

FineSim

Job description

Position:Sr. Staff Engineer, Analog/Mixed Signal Modelling and Verification

Location: Bengaluru, India

Job Id:696

# of Openings:0

Sr. Staff Engineer, Analog/Mixed Signal Modelling and Verification

Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.

Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.

We are seeking an exceptionally skilled and experienced Sr. Staff AMS Modelling and Verification Engineer, to join our Silicon Engineering team. In this senior role, you will be responsible for the behavioral modelling and verification of complex, high-performance integrated circuits, with a primary focus on custom analog, mixed-signal, and/or high-speed digital blocks. The ideal candidate is a recognized expert in mixed signal modelling and verification using system verilog RNM, verilog AMS for blocks such as PLLs, SerDes on the latest advanced semiconductor process nodes.

Key Responsibilities

• Work with architects to understand the requirements and functionality of mixed signal blocks.
• Independently develop test plans for mixed signal blocks.
• Work with the analog designers to understand the schematic and capture the most important parameters of the circuits in system verilog RNM, and their first and second order effects.
• Understand the functional requirements for mixed signal components and develop a behavioral model in terms of signal processing components using system verilog RNM
• Develop model vs schematic comparison using Cadence or Synopsys tool flows.
• Verify and sign-off on mixed signal RNM models.
• Help the SoC verification team in integrating the critical mixed signal IP into the full chip digital environment.
• Own and maintain these models through the lifecycle of the product.

Basic Qualifications

• Associates Degree, or equivalent experience
• 10+ years of hands-on analog/mixed signal verification experience with successful tapeouts
• 5+ years in SerDes verification
• A good understanding of high-speed design AMS verification.
• Deep knowledge of UVM, SystemVerilog-RNM, and Verilog-AMS.
• Advanced command of Cadence Virtuoso/Spectre/Xcelium or Synopsys VCS/FineSim.
• Proficient with Cadence and Synopsys AMS tools.

Preferred Qualifications

• Deep familiarity with high-speed analog/mixed-signal SerDes components.
• Experience with integration between custom AMS and digital components
• Advanced mastery of SystemVerilog-RNM (wreal, EEnet types) and Verilog-AMS
• Some knowledge of scripting languages such as Python and SKILL.
• Proven proficiency with advanced mixed-signal toolchains, including Cadence Spectre/Xcelium (AMS Designer) or Synopsys VCS/FineSim, alongside optical simulation tools (e.g., Ansys Lumerical, Synopsys OptoCompiler)
• Familiarity with UVM is desirable.
• Knowledge of Silicon Photonics is a plus.
• Excellent communication skills with the ability to clearly articulate complex technical issues and solutions to cross‑functional teams.