Sr. Engineer, ASIC Design Verification

Ayar Labs; Bengaluru; On-site; INR 800,000 - 1,500,000; Full time

Job summary

Ayar Labs in Bengaluru is seeking a Sr. Engineer - ASIC Design Verification to join their dynamic startup environment. This role involves pre-Si verification of complex SoCs, crafting design specifications, and developing verification methodologies.

The ideal candidate will have a strong background in ASIC verification with at least 2 years of experience in SystemVerilog and UVM testbench development. Responsibilities include managing projects with limited supervision and contributing to design for test methodologies.

Qualifications

• 2+ years of ASIC verification experience.
• 2+ years of SystemVerilog, UVM testbench development for design verification.
• 2+ years of scripting and/or programming skills.

Responsibilities

• Develop verification methodology and testbenches for digital and mixed‑signal blocks.
• Perform test plan, coverage analysis and closure for SerDes IP blocks.
• Design and contribute to design for test (DFT) methodologies.

Skills

ASIC verification experience

SystemVerilog

UVM testbench development

Scripting

Programming skills

Education

BS, MS in Electrical Engineering or Computer Engineering

Tools

NCSIM

VCS

ModelSim

Python

Job description

Location: Bengaluru, India

Job Id: 599

# of Openings: 0

Sr. Engineer - ASIC Design Verification

Location: Bangalor (on‑site, flexible hours)

Overview

Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co‑packaged optics (CPO), we use light instead of electricity to move data faster, further, and with a fraction of the energy required to fuel the explosive growth of AI models. Backed by industry giants such as NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ CPO solution is key to unleashing next‑generation AI scale‑up architectures.

This role is responsible for pre‑Si verification and validation of complex SoCs with both high‑speed custom and digital blocks. You will work in a dynamic startup environment as part of a small IC design team. An ideal candidate is a hands‑on self‑starter capable of crafting design specifications, verification suites and testbenches based on input from colleagues, customers and industry, and who can effectively manage their own time to take projects to completion with limited supervision.

Essential Functions

• Develop verification methodology and testbenches for digital and mixed‑signal blocks
• Test plan, coverage analysis and closure for parallel link and SerDes IP blocks and on‑chip interconnects
• Design and contribute to design for test (DFT) methodologies

Basic Qualifications

• BS, MS in Electrical Engineering, Computer Engineering or equivalent
• 2+ years of ASIC verification experience
• 2+ years of SystemVerilog, UVM testbench development for design verification of complex digital and PHY blocks (in AMS and WREAL modeling verification)
• 2+ years of scripting and/or programming skills

Preferred Qualifications

• Experience working on digital designs with multiple clock domains and clock dividers
• Post‑place‑and‑route functional verification (NCSIM, VCS, ModelSim)
• Experience in verification of SerDes IP block interfaces in a complex SoC fabric environment
• Experience in verification of the PCS, PMA SerDes layers and internal SerDes digital backends
• Experience with verification of HBM memory interfaces (PHY and controller)
• Experience in formal model equivalence checking tools and verification methodology
• Programming experience in Python