Sr. Engineer, Analog/Mixed-Signal Modelling and Verification

Ayar Labs, Inc.; Bengaluru; On-site; INR 2,600,000 - 4,200,000; Full time

Job summary

Ayar Labs is seeking an experienced Senior AMS Modelling and Verification Engineer to join its Silicon Engineering team in Bengaluru. The role focuses on behavioral modelling and verification of complex mixed-signal blocks, with emphasis on PLLs, SerDes, and high-speed digital IP.

You will develop RNM models in SystemVerilog, create test plans, and ensure model-vs-schematic accuracy using Cadence/Synopsys flows, collaborating with analog designers and the SoC verification team to integrate IP

Qualifications

• Associates Degree or equivalent experience required.
• 5–10+ years hands-on analog/mixed-signal verification with tapeouts.
• 2+ years in SerDes verification and high-speed AMS design understanding.

Responsibilities

• Understand requirements and functionality of mixed signal blocks.
• Develop test plans for mixed signal blocks.
• Capture key circuit parameters in system verilog RNM; assess first/second-order effects.
• Develop behavioral models for mixed signal blocks using RNM.
• Create model-vs-schematic comparisons using Cadence or Synopsys tool flows; provide feedback on mismatches.
• Verify and sign-off on RNM models for assigned blocks.
• Assist SoC verification teams to integrate mixed signal IP into the full chip environment.

Skills

Analog/mixed-signal verification

SystemVerilog RNM

Verilog-AMS

Cadence/Synopsys flows

UVM

Python scripting

Education

Associates Degree or equivalent

Tools

Cadence Virtuoso

Cadence Xcelium

Spectre

FineSim

Synopsys VCS

OptoCompiler

Ansys Lumerical

Job description

Senior Engineer, Analog/Mixed Signal Modelling and Verification

Location: Bengaluru (on-site, hours flexible)

Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.

Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.

We are seeking an experienced Senior AMS Modelling and Verification Engineer, to join our Silicon Engineering team. In this senior role, you will contribute to the behavioral modelling and verification of complex, high-performance integrated circuits, with a primary focus on custom analog, mixed-signal, and/or high-speed digital blocks. The ideal candidate has experience in mixed signal modelling and verification flows for mixed signals IPs such as PLLs, serdes, etc.

Key Responsibilities

• Understand the requirements and functionality of assigned mixed signal blocks.
• Develop test plans for mixed signal blocks.
• Work with the analog designers and the team lead to understand the schematic and capture the most important parameters of the circuits in system verilog RNM, and their first and second order effects.
• Develop a behavioral model for the mixed signal block in terms of signal processing components using system verilog RNM
• Develop model vs schematic comparison using Cadence or Synopsys tool flows. Provide continuous feedback to the team lead on model vs schematic mismatches.
• Verify and sign-off on mixed signal RNM models for the assigned blocks.
• Help the SoC verification team in integrating the critical mixed signal IP into the full chip digital environment.

Basic Qualifications

• Associates Degree, or equivalent experience
• 5-10+ years of hands-on analog/mixed signal verification experience with successful tapeouts
• 2+ years in SerDes verification
• A good understanding of high-speed design AMS verification.
• Experience in UVM, SystemVerilog-RNM, and Verilog-AMS.
• Experience with tools such as Cadence Virtuoso/Spectre/Xcelium or Synopsys VCS/FineSim.
• Familiar with Cadence and Synopsys AMS tools.

Preferred Qualifications

• Familiarity with high-speed analog/mixed-signal SerDes components.
• Experience with integration between custom AMS and digital components
• Experience in SystemVerilog-RNM (wreal, EEnet types) and Verilog-AMS
• Some knowledge of scripting languages such as Python and SKILL.
• Experience in advanced mixed-signal toolchains, including Cadence Spectre/Xcelium (AMS Designer) or Synopsys VCS/FineSim, alongside optical simulation tools (e.g., Ansys Lumerical, Synopsys OptoCompiler)
• Familiarity with UVM is desirable.
• Knowledge of Silicon Photonics is a plus.
• Team player