Sr. Principal Product Engineer – Digital & Signoff Group (DSG)

Cadence Design Systems; Bengaluru; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

Cadence Design Systems in Bangalore is seeking a Sr. Principal Product Engineer in the Digital and Signoff Group (DSG). You will bridge R&D, applications, and customers to shape the next generation of chip design software for 7nm and below.

As a senior technical leader, you will own P&R resources, drive timing closure, performance and area optimization, and collaborate with marketing to align roadmaps with customer needs.

Qualifications

• Bachelor's in Electronics Engineering with 8+ years of industry experience, or Master's with 6+ years in digital design.
• Deep knowledge of ASIC design flow RTL-to-GDSII with physical design and timing analysis.
• Hands-on timing closure and Power/Performance/Area optimization at 7nm or below.
• Proficiency with Tcl, Python, or Perl; familiarity with AI productivity tools is a plus.
• Strong communication to translate complex technical issues into actionable solutions.

Responsibilities

• Serve as the primary P&R resource for internal teams and external customers.
• Collaborate with R&D to diagnose and resolve software issues and ensure robust releases.
• Run design benchmarks to demonstrate Cadence's edge in PPA.
• Develop and deploy RTL-to-GDSII methodologies and scripts for customer goals.
• Partner with Product Marketing to align technical capabilities with market needs and customer roadmaps.

Skills

ASIC design flow

Physical design

Timing analysis

Tcl scripting

Python scripting

Perl scripting

Education

Bachelors in Electronics Engineering (EE)

Masters in Electronics Engineering (EE)

Tools

EDA tools (synthesis, placement, routing, signoff)

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Sr. Principal Product Engineer - Digital & Signoff Group (DSG)

Location: Bangalore

Team: Cadence DSG (Digital & Signoff Group)

The Opportunity

Join Cadence's Digital and Signoff Group (DSG) as a Product Engineer, where you will act as the vital bridge between R&D, Application Engineering, and our global customers. In this high-impact role, you will influence the next generation of chip design software, helping industry leaders solve complex physical design challenges at 7nm and below.

Key Responsibilities

• Technical Expert: Serve as the primary place-and-route (P&R) resource for internal development teams and external customers.
• Product Evolution: Collaborate with R&D to track, diagnose, and resolve software issues, ensuring a robust tool release cycle.
• Design Benchmarking: Execute competitive benchmarks to demonstrate Cadence's edge in Power, Performance, and Area (PPA).
• Flow Innovation: Develop and deploy customized RTL-to-GDSII methodologies and scripts to meet specific customer design goals.
• Strategic Collaboration: Partner with Product Marketing to align technical capabilities with market needs and customer roadmaps.

Requirements

• Education: Bachelors in Electronics Engineering (EE) + 8 or more years of industry experience, OR Masters in Electronics Engineering (EE) + 6 or more year of digital implementation experience.
• Core Expertise: Deep understanding of the full ASIC design flow (RTL-to-GDSII) with a focus on physical design and timing analysis.
• Advanced Node Experience: Proven hands-on experience with timing closure and PPA optimization at 7nm, 5nm, or below.
• Tool Proficiency: High familiarity with industry-standard EDA tools for synthesis, placement, routing, and signoff.
• Scripting Skills: Proficiency in Tcl, Python, or Perl (familiarity with AI-driven productivity tools is a major plus).
• Communication: Strong verbal and written skills to translate complex technical issues into actionable solutions.

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