Sr.Lead STA Engineer

Qualcomm; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Qualcomm India Private Limited in Bengaluru seeks a Sr.Lead (STA) Engineer to drive timing closure for SoC designs, working with RTL, CAD, DFT and PD teams.

You will perform STA across block, cluster and top levels, manage timing constraints, and provide actionable feedback to optimize frequency and power targets.

The role requires 5–9 years in STA, with Primetime and Tempus experience, and strong communication to lead the team and coordinate cross‑functional efforts.

Qualifications

• Bachelor’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• Master’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Responsibilities

• Work closely with RTL team to understand protocols, critical paths, and performance goals, and to define, implement, and validate timing constraints.
• Perform STA for high‑performance designs at block, cluster, and SoC/top‑level hierarchies across multiple modes, corners, and scenarios.
• Analyze timing on frequency‑critical paths and collaborate with RTL and DFT teams to drive logic and micro‑architectural fixes.
• Provide actionable timing feedback to block‑level and top‑level physical design engineers.
• Generate and review timing ECOs (logic and physical) to close setup, hold, noise, and cross‑talk violations.
• Lead the STA team for a given project.

Skills

STA

Timing closure

SoC timing

Multi-clock designs

Power targets

Scripting (Perl TCL AWK)

Education

Bachelor’s degree in Electrical/Electronics Engineering, Computer Science, or related field

Master’s degree in Electrical/Electronics Engineering, Computer Science, or related field

PhD in Computer Science, Electrical/Electronics Engineering, or related field

Tools

Primetime

Synopsys Tempus

DFT tools

Job description

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what is possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring‑up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting‑edge, world‑class products. Qualcomm Hardware Engineers collaborate with cross‑functional teams to develop solutions and meet performance requirements.

Minimum Qualifications

• Bachelor’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• Master’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Overview

As a Sr.Lead (STA) Engineer, you will be a key contributor to SoC level timing closure, working closely with RTL, CAD, DFT and physical design teams. You will drive timing analysis and closure for complex, multi‑GHz designs across block, cluster, and full‑chip hierarchies, ensuring aggressive frequency and power targets are met.

Roles and Responsibilities

• Work closely with RTL team to understand different protocols (DDR, PCIE, UCIE etc.), critical paths, and performance goals, and to define, implement, and validate timing constraints.
• Perform STA for high‑performance designs at block, cluster, and SoC/top‑level hierarchies across multiple modes, corners, and scenarios.
• Analyze timing on frequency‑critical paths and collaborate with RTL and DFT teams to drive logic and micro‑architectural fixes.
• Provide actionable timing feedback to block‑level and top‑level physical design engineers.
• Generate and review timing ECOs (logic and physical) to close setup, hold, noise, and cross‑talk violations.
• Lead the STA team for a given project.

Preferred Qualifications

• Bachelor’s or master’s degree in electrical/Electronic Engineering with 5-9 years of hands‑on experience in STA and timing closure.
• Strong experience with STA and timing closure for high‑performance SoCs.
• Expertise in multi‑clock, multi‑domain designs with aggressive frequency targets.
• Experience in deep sub‑micron technology nodes and advanced process technologies.
• Proven experience performing STA on large CPU/SoC designs with multi‑scenario and signoff‑quality closure.
• Familiarity with standard cell libraries, transistor fundamentals, and worst‑case corner selection for timing signoff.
• Strong understanding of industry‑standard synthesis and tape‑out flows.
• Excellent communication skills to work effectively with RTL designers, PD, and CAD teams.
• In‑depth knowledge of timing effects such as noise, cross‑talk, OCV/variation, and their impact on designs.
• Familiarity with both Tempus and Primetime STA tools.
• Familiarity with scripting languages like perl, tcl, awk, etc.

Equal Opportunity Employment

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. Please e‑mail [e-mail] or call Qualcomm’s toll‑free number. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process.