STA CAD Methodology Engineer, Sr Lead Bangalore, Karnataka, India Hardware Engineering Posted 8[...]

Qualcomm; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Qualcomm India Private Limited seeks an STA CAD Methodology Lead to own the next-gen static timing analysis flows. You will drive ECO convergence, timing closure strategies, and mentor a CAD team across complex SoC designs in advanced nodes.

You will collaborate with PNR, RTL, extraction, and technology groups to ensure first-time-right tapeouts. The role demands deep ASIC timing knowledge, 5+ years of hands-on STA experience, and expert scripting in TCL, Python, and Perl.

Qualifications

• BE/BTech/ME/MTech in VLSI or related field with 10+ years of experience.
• Hands-on STA constraints, timing analysis, and closure in large ASIC flows.
• Expertise with industry STA tools: PrimeTime, Tempus, and related TCL/Python scripting.
• Experience with PNR, extraction, and timing-driven optimization for advanced nodes.

Responsibilities

• Define, develop, and deploy industry-leading STA and ECO methodologies.
• Own end-to-end STA methodology from constraints to timing closure sign-off.
• Mentor a high-performing STA CAD team and drive automation and flow improvements.
• Collaborate with PNR, RTL, Extraction, and Technology teams to ensure convergence.

Skills

STA constraints

Timing analysis

PrimeTime

Tempus

Tcl scripting

Python scripting

Perl scripting

PNR

Extraction

3DIC Signoff

Die-to-Die

Hierarchical Timing

Education

BE/BTech or ME/MTech in VLSI

PhD in related field (optional)

Tools

Fishtail Timevision

Job description

## STA CAD Methodology Engineer, Sr LeadBangalore, Karnataka, IndiaApply NowFind out how well you match with this jobJob ID3093891## **Company:**Qualcomm India Private Limited## **Job Area:**Engineering Group, Engineering Group > Hardware Engineering**General Summary:**Job DescriptionWe are looking for a highly experienced **STA/Timing CAD Methodology Lead** to own, architect, and scale the next generation of static timing analysis methodologies for cutting‐edge, high‐performance SoC designs. In this role, you will be the technical force behind enabling robust STA flows, accelerating ECO convergence, and shaping the timing closure strategy for complex designs in advanced technology nodes.**Minimum Qualifications:**• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.Additional Job Description**What You Will Lead & Influence**As the STA CAD Methodology Lead, you will:* **Define, develop, and deploy** industry‐leading STA and ECO methodologies across multiple design teams.* **Drive continuous innovation** in timing flows, improving runtime, accuracy, and overall execution efficiency.* **Own end‐to‐end STA methodology**, from constraints development to timing closure sign‐off.* **Collaborate closely with PNR, RTL, Extraction, and Technology teams** to ensure smooth convergence at both block and top levels.* **Tackle complex timing challenges** on advanced nodes to guarantee first‐time‐right tapeouts with exceptional quality.* **Guide and mentor a high‐performing STA CAD team**, fostering a culture of excellence, ownership, and innovation.**Your Technical Expertise**We are looking for a leader with:* **Deep knowledge of the ASIC design cycle**, with strong expertise in timing closure flows and methodologies.* **5+ years of hands-on experience** in STA constraints, timing analysis, and closure.* **Expert-level proficiency** in industry-standard STA tools such as **PrimeTime, Tempus, Tweaker, PrimeClosure**.* Strong understanding of **advanced STA concepts**, OCV/POCV/AOCV, SI/IR implications, and timing bottlenecks at advanced nodes.* **Scripting mastery** in **TCL, Perl, Python**, enabling robust automation and flow enhancements.* Solid background in **PNR, extraction, and timing-driven optimization**.* Experience with **constraints verification tools** (e.g., Fishtail(TCM)/Timevision) - a strong plus.* Demonstrated **technical leadership skills** with the ability to influence, mentor, and lead a team.* Experience with Multi-die, Die-to-Die interfaces, and **3DIC Signoff** solutions preferred.* Knowledge of **Hierarchical Timing Signoff** (HyperScale/Boundary model) solutions**Qualifications*** **BE/BTech + 10 years** of experience, or* **ME/MTech + 10 years** of experience in VLSI, EDA, CAD, or related domains.**Applicants**: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.**To all Staffing and Recruiting Agencies**: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.