SoC STA/Timing Engineer, Staff

Qualcomm; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Qualcomm India Private Limited in Bengaluru seeks an experienced Hardware STA engineer to lead timing closure for multi‑mode, multi‑voltage SoC designs. You will set up and sign off STA flows, validate timing across PVT, and drive methodology across teams.

The role emphasizes back‑end flows and strong scripting skills. The candidate should possess 7–10 years of relavant experience, with hands‑on use of PrimeTime and Tempus and familiarity with ICC2/Innovus.

Qualifications

• Bachelor’s in CS/EE with 4+ years hardware engineering.
• Master’s in CS/EE with 3+ years hardware engineering.
• PhD in CS/EE with 2+ years hardware engineering.

Responsibilities

• STA setup & signoff for multi‑mode, multi‑voltage domain designs.
• Timing analysis & debug across multiple PVT using PrimeTime/Tempus.
• Flow optimization: run STA flows and correlate Spice to STA results.
• Methodology development: evaluate timing tools and automate STA/PD flows.
• Cross‑functional collaboration with design, DFT, synthesis, CAD teams.
• Low‑Power techniques: clock gating, power gating, multi‑voltage designs.
• ECO timing flow: handle timing ECOs and RTL‑to‑Netlist checks.

Skills

STA fundamentals

AOCV/POCV concepts

CTS

Timing constraints

Mentoring

TCL scripting

Perl scripting

Python scripting

Education

Bachelor's degree in CS/EE or related

Master's degree in CS/EE or related

PhD in CS/EE or related

Tools

PrimeTime

Tempus

ICC2

Innovus

Job description

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

Job Description:

• 7 to 10 years of relavant experience is a must
• STA Setup & Signoff: Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs for SoC & SubSystem
• Timing Analysis & Debug: Validate and debug timing across multiple PVT conditions using tools like PrimeTime and Tempus.
• Flow Optimization: Run STA flows and correlate Spice to STA results.
• Methodology Development: Evaluate timing methodologies/tools across technology nodes and automate STA/PD flows using TCL/Perl/Python.
• Cross-Functional Collaboration: Work closely with design, DFT, synthesis, technology, CAD and physical implementation teams.
• Low-Power Techniques: Knowledge of clock gating, power gating, and multi-voltage designs.
• ECO Timing Flow: Handle timing ECOs (DMSA, tweaker, PrimeClosure) and logical equivalence checks (RTL to Netlist).

Required Skills

• Strong expertise in STA fundamentals, AOCV/POCV concepts, CTS, and timing constraints.
• Hands-on experience with STA tools: PrimeTime, Tempus.
• Familiarity with ASIC back-end flows: ICC2, Innovus.
• Knowledge of signal integrity, cross-talk noise, and parasitic extraction.
• Scripting proficiency: TCL, Perl, Python.
• Mentoring junior engineers in different areas of timing flows and methodologies
• Understanding of Spice simulations: Hspice, FineSim, Monte Carlo analysis.

Preferred Experience

• Driving timing convergence at chip-level and hard-macro level.
• Exposure to RTL-to-GDSII flows.
• Good technical writing and communication skills for cross-team collaboration

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

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