Sr. Lead IP/RTL Design Engineer

AMD; India; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

AMD is seeking a Sr. Lead IP/RTL Design Engineer to architect, design and deliver Data Fabric IP RTL components, balancing power, performance and area for next‑gen SoCs.

You will collaborate with architecture, verification and physical design teams to achieve first‑pass silicon success, and you will guide execution teams with clear technical direction. The role involves leading design on multiple domains, refining timing targets, and mentoring junior engineers while ensuring quality and reliable

Qualifications

• Bachelor's or Master's degree in computer or electrical engineering.
• Strong NoC architecture and CPU/GPU coherency knowledge.
• Experience with ARM core interfacing and CHI protocol preferred.
• Knowledge of power management microarchitecture and low power design.

Responsibilities

• Define Data Fabric/NoC features to meet SoC requirements on power, performance and area.
• Drive specifications for data fabric IP blocks and provide technical direction.
• Lead discussions on ARM/x86 interfacing to AMD data fabric IPs.
• Lead design on one or more domains for the data fabric implementation.
• Identify complex issues/risks with architects and implement solutions.
• Mentor team and coordinate timing, verification and post-Si support.

Skills

NoC architecture

ARM core interfacing

Power optimization

Team leadership

CPU/GPU coherency

Communication skills

Education

Bachelor's or Master's in Computer/Electrical Engineering

Tools

Verilog

SystemVerilog

HDL design tools

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

Sr. Lead IP/RTL Design Engineer

THE ROLE:

As a member of the Data Fabric Team , you will help bring to life cutting-edge designs. Your role will be to micro-architect , design and deliver data fabric IP RTL components , while managing the requirements of power, performance and area , to meet next-gen fabric requirements. You will work closely with the architecture, Verification and Physical Design teams to achieve first pass silicon success.

THE PERSON:

A successful candidate will work with senior architects and design engineers. The candidate will be highly detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBILITIES:

• Define Data Fabric/ NoC features and capabilities required to meet SoC requirements on power, performance, Area targets.
• Close architecture and micro-architecture requirements, drive technical specifications for data fabric and its IP blocks to meet those requirements, and provide technical direction to execution teams
• Lead discussions on ARM/x86 core interfacing to AMD data fabric IPs, to match SoC requirements.
• Lead design on one or more domains for the data fabric implementation.
• Work with architects and design leads to identify and assess complex technical issues/risks and develop as well as implement solutions to achieve product requirements
• Knowledge sharing and mentoring
• Work closely with Design teams for Area refinement, Timing targets , Verification Test plan reviews, Pre-Si bug resolution and Performance/Power Verification sign offs
• Work closely with Verification teams to ensure quality component development
• Support Post-Si teams for functional issues debug/resolution

PREFERRED EXPERIENCE:

• Excellent foundation in NoC architecture and CPU/GPU coherency.
• Preferred expertise in ARM/other core architecture
• Preferred CHI protocol experience
• Experience analyzing NoC Fabric , CPU, or System-level Micro-Architectural features to identify performance bottlenecks within different workloads
• Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture and logic design
• Excellent communication skills.Ability to lead team technically.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering
• #LI-SR5

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.