Principal Cache RTL Design - CPU Team

AMD; Bengaluru; On-site; INR 4,000,000 - 8,000,000; Full time

Job summary

AMD is seeking a PMTS Silicon Design Engineer in Bengaluru with a deep passion for modern processor architecture and RTL design. You will contribute to high-performance x86-core features, IP integration, and power-management strategies while mentoring a design team.

The role requires extensive Verilog RTL experience, strong debugging and collaboration across DFT, Physical Design, and SOC teams, with a focus on design quality and multi-site coordination.

Qualifications

• 15+ years of experience in Digital IP/ASIC design and Verilog RTL development.
• Experience in full IP design cycle including requirements, architecture and microarchitecture.
• Expertise in RTL design verification, design quality checks, synthesis, timing closure and post-silicon validation.

Responsibilities

• RTL design of high-performance x86-core ISA features and IP integration.
• Architect and design power management, caches, and coherency.
• Optimize RTL for power-efficient IP; apply low-power techniques.
• Lead inter-IP integration issues and own clock-domain crossings.

Skills

Digital IP/ASIC design

Verilog RTL development

Design verification

Leadership & teamwork

Communication skills

Python/Perl scripting

Education

Master's degree in Electrical/Electronics Engineering, Computer Engineering, or VLSI design

Tools

Front-end EDA tools

RTL design verification tooling

Python/Perl scripting

Job description

Job Description:

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you will discover the real differentiator is our culture. We push the limits of innovation to solve the worlds most important challenges - striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

PMTS SILICON DESIGN ENGINEER

THE PERSON

You have a passion for modern, complex processor architecture, digital design as well as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem-solving skills and are willing to learn and ready to take on problems. A global mindset and ability to work in a multi-site environment are keys to being successful in this role.

KEY RESPONSIBILITIES

• RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design
• Architect and design of power management features, cache, coherency.
• Design optimization for implementing power efficient IP, implementing the RTL using low power techniques
• Responsible for the inter IP integration issues resolution
• Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem.
• Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design
• Architecting, micro-architecting and documentation of the design features
• Lead design team from all aspects of the RTL deliverables.
• Mentor the junior members of the RTL team to meet the team goals
• Represents AMD to the outside technical community, partners and vendors
• Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion.

Preferred Experience

• 15+ years of experience in Digital IP/ASIC design and Verilog RTL development
• Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification.
• Should be well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation.
• Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects.
• Should possess expertise in front-end EDA tools sign-off and its flows.
• Familiarity with low power design and low power flow is an added plus.
• Ability to program with scripting languages such as Python or Perl is a plus;
• Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements;
• Proven interpersonal skills, leadership and teamwork;
• Excellent writing skills in the English language, editing and organizational skills required;
• Skilled at prioritization and multi-tasking;
• Good understanding of engineering terminology used within the semiconductor industry;
• Good understanding of digital design concepts;
• Knowledge of, or experience in, functional design verification or design is highly desired.

Academic Credentials

Master's degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or VLSI design Engineering.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available here.

This posting is for an existing vacancy.