SoC Physical Design Professional

QUALCOMM, Inc.; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Qualcomm India Private Limited is seeking a Hardware Engineer to plan, design, verify, and test complex SoCs and subsystems. You will lead physical design efforts across full-chip and sub-system scopes, collaborating with cross-functional teams to achieve aggressive silicon schedules and reliable delivery.

The role emphasizes floorplanning, power integrity, placement, routing, timing closure, and low-power design, with experience on advanced nodes and industry tools. Bangalore-based position.

Qualifications

• Bachelor's degree with 6+ years hardware engineering or related work experience.
• Master's degree with 5+ years hardware engineering or related work experience.
• PhD with 4+ years hardware engineering or related work experience.
• Hands-on ASIC/SoC physical design experience with multiple tapeouts.

Responsibilities

• Lead end-to-end physical design for large-scale SoCs and subsystems from architecture to tapeout.
• Own full-chip design strategy including Floorplanning, PDN, Placement, CTS, Routing, Timing Closure.
• Drive PPA optimization and signoff across process nodes.
• Define and improve physical design methodologies and automation flows.
• Collaborate with Architecture, RTL, STA, DFT, Package, CAD, and Product teams to meet silicon schedules.
• Resolve timing, congestion, IR/EM, noise, and manufacturability issues.
• Provide leadership during tapeout planning and silicon delivery.

Skills

ASIC/SoC PD

Floorplanning

Power Delivery

Placement

CTS

Routing

Timing Closure

Signal Integrity

IR/EM Analysis

Physical Verification

Education

Bachelor's degree in CS/EE

Master's degree in CS/EE

PhD in CS/EE

Tools

Innovus

ICC2/Fusion Compiler

PrimeTime

Tempus

Calibre

RedHawk

Voltus

Job description

Company: Qualcomm India Private Limited

Job Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Experience: 3+ Years
Location: Bangalore

Job Responsibilities

• Lead end-to-end physical design implementation for large-scale SoCs and complex subsystems, driving projects from architecture definition to successful tapeout.
• Own full-chip and subsystem physical design strategy including Floorplanning, Power Planning (PDN), Placement, CTS, Routing, Timing Closure, Signal Integrity, and Physical Verification.
• Drive PPA (Performance, Power, Area) optimization and signoff closure across advanced process nodes.
• Define and enhance physical design methodologies, automation flows, and best practices to improve design efficiency and quality.
• Lead cross-functional collaboration with Architecture, RTL, STA, DFT, Package, CAD, Technology, and Product Engineering teams to achieve aggressive silicon schedules.
• Resolve complex design challenges involving timing convergence, congestion, IR/EM, noise, reliability, and manufacturability.
• Provide technical leadership during tapeout planning and execution, ensuring high-quality silicon delivery.
• Mentor and guide junior engineers, driving technical excellence across the organization.
• Influence future design methodologies and contribute to strategic technology roadmap decisions.

Required Skills

• 3+ years of hands-on experience in ASIC/SoC Physical Design with proven success across multiple tapeouts.
• Deep expertise in Floorplanning, Power Delivery Networks, Placement, CTS, Routing, Timing Closure, Signal Integrity, IR/EM Analysis, and Physical Verification.
• Strong understanding of advanced signoff methodologies including STA, SI, Power Integrity, Reliability, DRC/LVS, ERC, PERC, and ESD verification.
• Extensive experience with industry-standard EDA tools such as Innovus, ICC2/Fusion Compiler, PrimeTime, Tempus, Calibre, RedHawk, Voltus, and related signoff tools.
• Proven experience leading physical design execution on advanced technology nodes (5nm, 3nm, or equivalent).
• Strong expertise in low-power design methodologies, power-aware implementation, and multi-voltage designs.
• Demonstrated ability to drive technical decisions, solve complex design challenges, and influence cross-functional teams.
• Excellent leadership, communication, and stakeholder management skills.

Preferred Qualifications

• Experience in high-performance CPU, GPU, AI/ML, Mobile, Networking, Datacenter, or Multimedia SoCs.
• Demonstrated ownership of full-chip physical design and successful delivery of complex SoCs to production.
• Experience driving methodology development, flow automation, and design productivity improvements.
• Prior experience leading and mentoring teams of Physical Design engineers.
• Candidates from leading semiconductor product companies are strongly preferred.