SoC Physical Design Bangalore, India Hardware Engineering Posted 11 hours ago

QUALCOMM, Inc.; Bengaluru; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

Qualcomm India Private Limited is seeking a seasoned Hardware Engineer to lead end-to-end physical design for large-scale SoCs in Bangalore. You will drive floorplanning, power integrity, placement, CTS, routing and timing closure while coordinating with architecture, RTL, and signoff teams to meet aggressive silicon schedules.

The role emphasizes low-power design, signoff methodologies, and collaboration across multiple engineering functions for high-performance SoCs on advanced process nodes.

Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering or related field with 6+ years hardware engineering experience; or Master's with 5+ years; or PhD with 4+ years.

Responsibilities

• Lead end-to-end physical design implementation for large-scale SoCs and complex subsystems.
• Own full-chip and subsystem physical design strategy including Floorplanning, PDN, Placement, CTS, Routing, Timing Closure, SI, and Physical Verification.
• Drive PPA optimization and signoff closure across advanced nodes.
• Define and enhance physical design methodologies, automation flows, and best practices.
• Lead cross-functional collaboration with Architecture, RTL, STA, DFT, Package, CAD, Technology, and Product Engineering teams.

Skills

ASIC/SoC PD

Floorplanning

Power delivery

Placement

CTS

Routing

Timing closure

Signal integrity

Physical verification

STA

DRC/LVS

Innovus

ICC2/Fusion Compiler

PrimeTime

Tempus

Calibre

RedHawk

Voltus

5nm/3nm

Low-power design

Education

Bachelor's degree in CS/EEE

Master's degree in CS/EE

PhD in CS/EE

Tools

Innovus

ICC2/Fusion Compiler

PrimeTime

Tempus

Calibre

RedHawk

Voltus

Job description

## SoC Physical DesignBangalore, IndiaApply NowFind out how well you match with this jobJob ID: 3096920## **Company:**Qualcomm India Private Limited## **Job Area:**Engineering Group, Engineering Group > Hardware Engineering**General Summary:**As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.**Minimum Qualifications:**• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.**Experience:**3+ Years **Location:** Bangalore **Job Responsibilities:*** Lead end-to-end physical design implementation for large-scale SoCs and complex subsystems, driving projects from architecture definition to successful tapeout.* Own full-chip and subsystem physical design strategy including Floorplanning, Power Planning (PDN), Placement, CTS, Routing, Timing Closure, Signal Integrity, and Physical Verification.* Drive PPA (Performance, Power, Area) optimization and signoff closure across advanced process nodes.* Define and enhance physical design methodologies, automation flows, and best practices to improve design efficiency and quality.* Lead cross-functional collaboration with Architecture, RTL, STA, DFT, Package, CAD, Technology, and Product Engineering teams to achieve aggressive silicon schedules.* Resolve complex design challenges involving timing convergence, congestion, IR/EM, noise, reliability, and manufacturability.* Provide technical leadership during tapeout planning and execution, ensuring high-quality silicon delivery.* Mentor and guide junior engineers, driving technical excellence across the organization.* Influence future design methodologies and contribute to strategic technology roadmap decisions. **Required Skills*** **3+ years of hands-on experience in ASIC/SoC Physical Design with proven success across multiple tapeouts.*** Deep expertise in Floorplanning, Power Delivery Networks, Placement, CTS, Routing, Timing Closure, Signal Integrity, IR/EM Analysis, and Physical Verification.* Strong understanding of advanced signoff methodologies including STA, SI, Power Integrity, Reliability, DRC/LVS, ERC, PERC, and ESD verification.* Extensive experience with industry-standard EDA tools such as Innovus, ICC2/Fusion Compiler, PrimeTime, Tempus, Calibre, RedHawk, Voltus, and related signoff tools.* Proven experience leading physical design execution on advanced technology nodes (5nm, 3nm, or equivalent).* Strong expertise in low-power design methodologies, power-aware implementation, and multi-voltage designs.* Demonstrated ability to drive technical decisions, solve complex design challenges, and influence cross-functional teams.* Excellent leadership, communication, and stakeholder management skills. **Preferred Qualificatio**ns:* Experience in high-performance CPU, GPU, AI/ML, Mobile, Networking, Datacenter, or Multimedia SoCs.* Demonstrated ownership of full-chip physical design and successful delivery of complex SoCs to production.* Experience driving methodology development, flow automation, and design productivity improvements.* Prior experience leading and mentoring teams of Physical Design engineers.* Candidates from leading semiconductor product companies are strongly preferred.**Applicants**: Qualcomm is an equal opportunity employer. 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