Physical Verification Engineer (Lead/Staff/Sr Staff)

QUALCOMM, Inc.; Bengaluru; Presencial; INR 4.000.000 - 7.000.000; Jornada completa

Descripción de la vacante

Qualcomm India Private Limited seeks a Hardware Engineer to plan, design, verify and test electronic systems across Digital/Analog/RF and packaging. You will collaborate with cross-functional teams to ensure sign-off quality and robust physical implementation.

The role emphasizes experience with physical verification flows, PDk concepts, and leading toolchains like Innovus and Calibre across 2nm–10nm nodes. A strong debugging mindset and automation interest are valued.

Formación

• Experience with physical verification sign-off flows and toolchains.
• Strong understanding of PDk concepts, SVRF, Calibre and ICV.
• Hands-on with implementation tools like Innovus and Fusion Compiler.

Responsabilidades

• Drive Physical Verification sign-off activities for advanced nodes.
• Collaborate with PD, layout, and foundry teams for sign-off and convergence.
• Debug and drive closure of sign-off violations to tape-out.
• Support methodology development, automation, and flow improvements for quality.
• Participate in floorplanning, power planning, and PDN reviews.

Conocimientos

Physical Verification sign-off flows

PDK concepts, SVRF rule decks, Calibre

Innovus ICC2 Fusion Compiler

Physical Design implementation flow

Advanced technology nodes (2nm-10nm)

Tech LEF, Design Rules, Foundry PDKs

Debugging sign-off environments

Educación

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field

Herramientas

Innovus

ICC2

Fusion Compiler

Calibre

Descripción del empleo

Company: Qualcomm India Private Limited

Job Area: Engineering Group, Engineering Group > Hardware Engineering

Job Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
• OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
• OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Experience

5 to 15 Years

Key Responsibilities

• Drive Physical Verification sign-off activities including DRC, LVS, Antenna, ERC, PERC, ESD, and related verification checks for advanced technology nodes.
• Collaborate closely with Physical Design, Custom Layout, and Foundry teams to ensure clean sign-off and physical convergence.
• Debug and resolve physical verification violations while driving closure to tape-out.
• Support methodology development, automation, and flow enhancements for sign-off quality and productivity.
• Participate in floorplanning, power planning, and PDN reviews to ensure robust physical implementation.

Required Skills

• Strong experience with Physical Verification sign-off flows and tools.
• Good understanding of PDK concepts, SVRF rule decks, Calibre, and ICV.
• Hands-on experience with Innovus, ICC2, Fusion Compiler, or equivalent implementation tools.
• Solid understanding of Physical Design implementation flow, layouts, and backend design methodologies.
• Experience working on advanced technology nodes such as 2nm, 3nm, 5nm, 7nm, or 10nm.
• Familiarity with Tech LEF, Design Rules, and Foundry PDKs.
• Strong debugging and problem-solving skills in sign-off environments.

Preferred Qualifications

• Experience in Floorplanning, Power Planning, and PDN design.
• Team leadership or people management experience.
• Automation skills using TCL, Perl, or scripting languages.
• Exposure to custom IC design flows and mixed-signal/SOC environments.

Nice to Have

• Experience driving physical convergence across multiple blocks or full-chip designs.
• Exposure to ESD reliability analysis and advanced PERC methodologies.
• Experience mentoring junior engineers and leading technical initiatives.