SoC Edge-AI Design Verification Engineer, Google Cloud

Google; Hyderabad; On-site; INR 1,200,000 - 2,100,000; Full time

Job summary

Google LLC is seeking a verification engineer to join its AI and Infrastructure hardware team in Hyderabad. You will build verification components, run constrained-random tests, and drive verification closure for ASIC/FPGA designs.

You will collaborate with design and verification engineers on projects, verify digital designs, and manage the full life-cycle from planning to coverage closure. This role emphasizes in-person collaboration and rigorous verification practices to deliver highly

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 4 years of verification experience in standard methodologies.

Responsibilities

• Plan verification of digital design blocks by understanding specifications and coordinating with design engineers.
• Create and enhance constrained-random verification environments using SystemVerilog/UVM or formally verify designs with SystemVerilog Assertions (SVA) and formal tools.
• Identify and write all types of coverage measures for corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.

Skills

SystemVerilog

Verification environments

Constrained-random testing

UVM

RTL verification

Specman/E

ASIC verification

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

UVM

Specman/E

Job description

X In most instances, this position requires in-person interviews as part of the hiring process.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Hyderabad, Telangana, India.

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 4 years of experience creating and using verification components and environments in standard verification methodology.
• Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, or a related field.
• Experience creating and using verification components and environments in a standard verification methodology (e.g., UVM).
• Experience with verification techniques, and the full verification life cycle.
• Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
• Experience with performance verification of ASICs and ASIC components.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
• Identify and write all types of coverage measures for corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.