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Angel and Genie is seeking a senior DFT architect to own SoC-level DFT architecture and strategy. You will drive implementation plans across multiple concurrent programs, acting as the technical authority for all DFT decisions and signoffs while mentoring a team of engineers.
Collaboration with RTL, STA, PD, and manufacturing ensures DFT readiness from design to tapeout. Strong leadership and communication are essential.
SoCDFTArchitecture&Leadership
OwnSoC-levelDFTarchitectureandstrategyforcustomandplatform-basedSoCs.
DefineanddriveDFTimplementationplansacrossmultipleconcurrentSoCprograms.
ActasthetechnicalauthorityandsignoffownerforallDFT-relateddecisionsanddeliverables.
LeadDFTRTLintegration,scaninsertion,andtestarchitectureimplementation.
Ownanddrive:
Scan,Compression,andATPGstrategy
MBIST,BISR,andredundancyimplementation
JTAG/TAP,BoundaryScan,anddebuginfrastructure
EnsureDFTreadinessacrossfunctional,scan,andlow-powermodes.
CollaboratewithRTL,STA,andPDteamstoensureDFT-friendlydesignandimplementation.
DriveATPGpatterngeneration,simulation,anddebugtoensurehightestcoverageandquality.
WorkcloselywithphysicaldesignteamstoensurescanandtestlogicclosurewithminimalPPAimpact.
Interfacewithmanufacturing,ATE,andOSATteamsontestrequirements,vectordelivery,andsiliconbring-up.
Supportpost-silicondebug,yieldramp,andtestoptimization.
RepresentSemifiveincustomer-facingtechnicaldiscussionsrelatedtoDFTstrategyandsignoff.
DefineandstandardizeDFTmethodologies,flows,andchecklistsacrossSemifiveprograms.
Driveautomation,scripting,andreusetoimproveDFTefficiencyandpredictability.
MentoranddevelopDFTengineersandleads,buildingdeeptechnicalandexecutioncapability.
ReviewandapproveDFTsignoffreportsandtapeoutreadinesscriteria.
B.E./B.TechorM.E./M.TechinElectrical/Electronics/VLSIEngineering.
12+yearsofexperienceinDFTarchitectureandimplementationforcomplexSoCs.
ProventrackrecordofleadingDFTimplementationandsignoffonmultiplecustomSoCtapeouts.
Scan,Compression,andATPGmethodologies
MBIST,BISR,andmemoryrepairschemes
JTAG/TAPandBoundaryScan
DFTRTLintegrationandpatternsimulation
Hands-onexperiencewithindustry-standardDFTtools,suchas:
SiemensTessent
SynopsysDFTMAX/TestMAX
SpyGlassDFT(orequivalent)
Strongunderstandingof:
Low-powerDFTchallenges(UPF/CPF)
Scanandtest-modetimingclosure
PhysicalimplementationconstraintsforDFT
Experienceworkingwithmanufacturing,ATE,andpost-siliconvalidationteams.
Excellentproblem-solving,communication,andleadershipskills.