Silicon Validation Manager

Kandou AI; Hyderabad; On-site; INR 4,000,000 - 7,000,000; Full time

Benefits offered by this job

Equity participation

Flexible work arrangements

Competitive compensation

Job summary

Kandou AI is seeking a seasoned Silicon Validation Lead to own end-to-end validation for next-generation SoC platforms, integrating PCIe, CXL, DDR5, and RoT subsystems. You will guide a cross-functional team, define test strategies, and drive production-ready validation.

You will collaborate with RTL, DV, firmware, and software groups to ensure smooth handoffs from pre-silicon validation to physical silicon verification, leveraging a range of test equipment and automation tools.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 10+ years of hands-on silicon validation or hardware validation experience, with at least 2 years in a Lead or staff-level role.
• Deep expertise in PCIe (Gen 4/5/6): protocol-level knowledge, compliance testing, physical layer characterization, and debug.
• Strong hands-on experience with CXL (1.1/2.0/3.0): memory semantic protocols, device types, coherency mechanisms, and interoperability testing.
• Extensive experience validating DDR5 memory subsystems: timing margins, signal integrity, JEDEC compliance, and RAS features.
• Solid experience with RISC-V processor bring-up, ISA compliance validation, and core/cluster debug using JTAG and hardware debug probes.
• Hands-on experience with Memory Fabric architectures: bandwidth/latency characterization, coherency validation, and fabric stress testing.
• Experience validating PCIe Switch silicon: multi-port topologies, QoS, hot-plug, and error-handling scenarios.
• Experience with Caliptra RoT or equivalent security subsystem validation: secure boot, firmware attestation, cryptographic engine verification.

Responsibilities

• Own the full lifecycle of silicon bring-up and validation for next-generation SoC platforms with PCIe, CXL, DDR5, RISC-V cores, and RoT subsystems.
• Lead a cross-functional validation team; define test strategies, coverage, and sign-off criteria.
• Develop validation collateral: test plans, test suites, regression frameworks, and pass/fail criteria.
• Drive lab infrastructure: board bring-up environments, FPGA prototypes, simulation correlation, and lab automation frameworks.
• Establish dashboards for coverage tracking and triage to reduce validation escapes.
• Lead deep-dive debugging across RTL, firmware, hardware, and system software using advanced instruments.

Skills

PCIe expertise

CXL expertise

DDR5 validation

RISC-V bring-up

Silicon validation leadership

System verification

Education

Bachelor's or Master's in Electrical/Computer Engineering or Computer Science

Tools

Protocol analyzers

Oscilloscopes

BERT

VNAs

JTAG debugging

OpenOCD

GDB

Python

Tcl

Bash

PyATS

Robot Framework

Job description

https://www.thecube.net/events/nyse/ai-factory-data-center-of-the-future/content/Videos/d1ad8af3-1424-4336-a9b3-1d02b5a354b4

we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale

.

our architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.

Department: Silicon Engineering / Hardware Validation

Employment Type: Full-

Time

We are a semiconductor company pioneering high-performance interconnect and chip-tochip communication solutions.

Our engineering teams push the boundaries of what is possible in silicon design, validation, and system integration.

We are looking for a seasoned Silicon Validation Lead to join our R&D organization and drive end-to-end validation of complex SoC platforms.

Role Overview

As the Silicon Validation Director you will own the full lifecycle of silicon bring-up and validation for next-generation SoC platforms that integrate PCIe, CXL, DDR5, RISC-V processors, Memory Fabric, PCIe Switch, and Caliptra Root of Trust (RoT) subsystems.

You will lead a cross-functional validation team, define test strategies, and act as the primary technical interface between design, architecture, firmware, and system teams to ensure first-pass silicon quality and robust production readiness.

Key Responsibilities

Silicon Bring-Up & Validation Lead pre- and post-silicon validation for complex SoCs encompassing PCIe Gen 4/5/6, CXL 1.1/2.0/3.0, DDR5 memory subsystems, RISC-V processor cores, Memory Fabric, PCIe Switch, and Caliptra RoT IP.

Drive silicon bring-up from power-on through full functional validation, characterization, and compliance testing. Develop and own comprehensive silicon validation plans, test coverage matrices, and sign-off criteria aligned with tapeout and production mlestones.

Execute and manage compliance and interoperability testing against PCIe, CXL, JEDEC DDR5, and relevant security/RoT standards. Test Architecture & Strategy

Define test infrastructure architecture: board-level bring-up environments, FPGA prototypes, simulation correlation, and lab automation

frameworks.

Drive development of validation collateral including test plans, test suites, regression frameworks, and pass/fail criteria for all integrated subsystems.

Establish coverage tracking dashboards and triage processes to systematically reduce validation escapes. Debug & Root

Lead deep-dive debugging of complex multi-layer failures spanning RTL, firmware, hardware, and system software.

Utilize protocol analyzers, logic analyzers, oscilloscopes, and CXL/PCIe test equipment (e.g., Teledyne LeCroy, Keysight, Spirent) to isolate and characterize issues.

Author and maintain detailed bug reports, failure analysis documents, and errata for silicon revisions.

Team Leadership & Collaboration

Lead and mentor a team of validation engineers; set technical direction, review deliverables, and foster a culture of engineering rigor.

Collaborate closely with RTL design, DV, firmware, and software teams to ensure seamless hand-off from pre-silicon simulation to physical silicon validation.

Interface with external IP vendors, OEM/ODM partners, and compliance labs for interoperability and certification activities.

Represent the validation team in architecture reviews, design reviews, and program planning meetings.

Process & Continuous Improvement

Champion test automation and CI/CD integration for regression management.

Drive lessons-learned processes across silicon spins and contribute to validation methodology improvements.

Establish and maintain lab safety, equipment inventory, and test asset management best practices.

Required Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

10+ years of hands-on silicon validation or hardware validation engineering experience, with at least 2 years in a Lead or staff-level role.

Deep expertise in PCIe (Gen 4/5/6): protocol-level knowledge, compliance testing, physical layer ch

aracterization, and debug.

Strong hands-on experience with CXL (1.1 / 2.0 / 3.0): memory semantic protocols, device types (Type 1/2/3), coherency mechanisms, and interoperability testing.

Extensive experience validating DDR5 memory subsystems: timing margins, signal integrity, JEDEC compliance, and RAS features.

Solid experience with RISC-V processor bring-up, ISA compliance validation, and core/cluster debug using JTAG and hardware debug probes.

Hands-on experience with Memory Fabric architectures: bandwidth/latency characterization, coherency validation, and fabric stress testing.

Experience validating PCIe Switch silicon: multi-port topologies, QoS, hot-plug, and error-handling scenarios. Experience with Caliptra Root of Trust or equivalent security subsystem validation: secure boot, firmware attestation, cryptographic engine verification, and DICE/RoT compliance

.

Technical Skills Domain

Skills

Protocols

CXL1.1/2.0/3.0,

DDR5,

Processor RISC-V (RV64GC, RISC-V Debug Spec),JTAG Security Caliptra RoT, Secure Boot, DICE, TPM concepts Interconnect Memory Fabric, PCIe Switch,

Instrumentation Protocol analyzers, BERT,

oscilloscopes, VNAs

AutomationPython, Tcl, Bash, PyATS, Robot Framework EDA / Debug Signal Tap, Chip

Scope, OpenOCD, GDB

What We Offer

Opportunity to work on cutting-edge, industry-defining interconnect and semiconductor technology.

Collaborative, high-trust engineering culture with direct access to architecture and design teams.

Competitive compensation, equity participation, and comprehensive benefits.

Flexible work arrangements and a commitment to continued technical growth.

We are an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we