SI/PI Engineer

Sense; Bengaluru; On-site; INR 1,200,000 - 2,200,000; Full time

Job summary

Sense in Bengaluru, India seeks an SI/PI engineer to drive channel modeling, extraction and eye analysis for high-speed interfaces. You will perform pre-layout and post-layout simulations, assess crosstalk, jitter and TDR, and optimize PDN for high-current ASICs and FPGAs.

You will apply tools like HFSS, Siwave and HyperLynx, work with automotive standards, and deliver design guidelines with clear, actionable reports based on your simulations.

Qualifications

• Signal integrity and power integrity concepts for high-speed interfaces.
• Hands-on experience with HFSS, Siwave, Altium Designer and HyperLynx.
• Familiarity with JEDEC, LPDDR4/LPDDR5, PCIe 4/5, GMSL, FPD-Link, MIPI-CSI, USB, Ethernet automotive standards.
• Ability to perform board-level timing analysis using tools.
• Strong analytical, problem-solving and documentation skills.

Responsibilities

• Perform channel modeling, extraction and eye analysis for high-speed interfaces.
• Conduct pre-layout and post-layout SI simulations to ensure compliance with interface standards.
• Analyze crosstalk, reflections, jitter, insertion loss, return loss and TDR.
• Model, analyze and provide recommendations on board PDN.
• Perform AC/DC droop analysis and target impedance profiling for power delivery to ASICs, SoCs and FPGAs.
• Collaborate with Hardware and ECAD teams to optimize signal and power integrity.
• Provide design guidelines balancing SI and PI constraints.
• Generate technical reports and provide design recommendations based on simulations.

Skills

Signal integrity

Power integrity

Timing analysis

MIPI-CSI

Automotive standards

JEDEC

PCIe 4/5

LPDDR4/LPDDR5

Tools

Ansys HFSS

Ansys Siwave

Altium Designer

Siemens HyperLynx 2D/3D

Job description

• Perform channel modeling, extraction, and eye analysis for high-speed interfaces.
• Conduct pre-layout and post-layout SI simulations to ensure compliance with interface standards.
• Analyze crosstalk, reflections, jitter, insertion loss, return loss and TDR.
• Model, analyze and provide recommendations on board PDN.
• Perform AC/DC droop analysis, target impedance profiling to ensure clean power delivery to high-current ASICs, SoCs, and FPGAs.
• Collaborate with Hardware and ECAD teams to optimize signal integrity and power integrity performance.
• Provide design guidelines balancing both SI and PI constraints.
• Generate technical reports and provide design recommendations based on simulation results.

Job Requirement

• Strong understanding of signal integrity and power integrity concepts for high-speed serial and memory interfaces.
• Hands-on experience with: Ansys HFSS, Altium Designer, Ansys Siwave, Siemens hyperlynx 2D & 3D.
• Familiarity with JEDEC, LPDDR4/LPDDR5, PCIe 4/5, GMSL, FPD -Link, MIPI-CSI, USB, Ethernet and other automotive standards.
• Ability to perform board level timing analysis using tools.
• Strong analytical and problem-solving skills with good communication and documentation skills.