Principal Engineer, System HW Design - SI/PI

SiMa.ai; Bengaluru; On-site; INR 3,600,000 - 7,200,000; Full time

Job summary

SiMa.ai is seeking a Principal Engineer, System HW Design - SI/PI in Bangalore, India to lead the SI/PI strategy across the MLSoC product line, including SoM, PCIe cards, and reference designs. You will define architecture, drive impedance and PDN targets, and coordinate with vendors for reliable high-speed signaling and power delivery.

The role requires deep expertise in PCIe Gen4/Gen5, DDR4/DDR5/LPDDR, MIPI, USB, and high-speed measurement techniques, with hands-on lab validation and

Qualifications

• Bachelors in Electrical Engineering or related field; Master's preferred.
• Experience leading SI/PI strategy across multiple programs.
• Expertise with PCIe Gen4/Gen5, DDR4/DDR5/LPDDR, USB/MIPI signaling.

Responsibilities

• Define and document SI/PI architecture, design guidelines, and sign-off criteria.
• Own power delivery network architecture for high-transient AI accelerators.
• Drive stack-up, impedance, and channel budget decisions across boards.
• Lead lab validation standards and escalation-level debug for bring-up issues.
• Oversee SI/PI tool strategy and reusable methodology assets.

Skills

PCIe Gen4/Gen5 signaling

DDR4/DDR5/LPDDR signaling

MIPI CSI/DSI signaling

High-speed PCB/SI/PI

PDN architecture

Lab validation & debugging

PCB stack-up design

Cross-functional leadership

Signal integrity modeling

Education

Bachelor's in Electrical Engineering

Master's degree preferred

Tools

Ansys HFSS/SIwave

Cadence Sigrity/Clarity

Keysight ADS

Job description

Job Title: Principal Engineer, System HW Design - SI/PI

Job Location: Bangalore, India (This position requires a full-time, on-site presence in our Bangalore, India Office)

Job ID: AI2545

As Principal Engineer, System HW Design - SI/PI, you will be part of the Systems Hardware Engineering Team that designs, builds, brings-up, and productizes PCB boards for SiMa.ai. This showcases SiMas MLSoC Machine Learning SoC across bring-up and debug, characterization, customer samples, and eventual production. In this role, you will define and drive SI/PI strategy across our entire MLSoC product line - spanning System-on-Module designs, PCIe add-in cards, chip-down BGA reference designs, and full development platforms. This is a significant technical contributor role that will define how signal and power integrity (SI/PI) is implemented across the hardware organization. Working with internal teams and external vendors, the role will guide PCB design, simulation, and lab validation to ensure reliable high-speed signaling and power delivery across our hardware platforms.

Role responsibilities

• Define, document (including simulation reports and design decisions),own SI/PI architecture, design guidelines, review processes, and sign-off criteria across the full SiMa.ai product portfolio (SoM, PCIe HHHL card, chip-down BGA design, DevKit carrier, and future platforms).
• Serve as the technical specialist on high-speed interface margin closure: PCIe Gen5 (root complex, up to 32 GT/s/lane), MIPI CSI/DSI (C-PHY/D-PHY), USB 3.x/Type-C, 10 Gigabit Ethernet SerDes, and LPDDR memory channels
• Drive stack-up, impedance, and channel budget decisions across concurrent board programs, resolving trade-offs between cost, manufacturability, and signal margin at the product-line level
• Own power delivery network (PDN) architecture for high-transient-current AI accelerator silicon, setting design targets and review standards used across all boards
• Set the long-term connector/interconnect strategy across product generations (board-to-board, M.2 NVMe, PCIe edge-card interfaces)
• Define lab validation standards and own escalation-level debug for the hardest SI/PI bring-up issues across programs
• Own the SI/PI simulation tool strategy and flow (Ansys HFSS/SIwave, Cadence Sigrity/Clarity, Keysight ADS, or equivalent) - evaluate and select tools, and build reusable methodology assets for the team
• Own or support compliance testing (PCIe-SIG, USB-IF, MIPI Alliance) for interfaces on production and pre-production boards
• Engage with component/module vendors and standards bodies as needed to stay ahead of emerging high-speed interface requirements

Minimum Requirements

• Bachelors in Electrical Engineering or a related field. Master s degree preferred with 15 years of industry experience in signal integrity and power integrity engineering for high-speed digital systems, including experience leading SI/PI strategy across multiple concurrent programs
• Deep, demonstrated expertise with PCIe Gen4/Gen5, DDR4/DDR5/LPDDR, USB 3.x, and MIPI D-PHY/C-PHY signaling, including having driven margin closure on production designs
• Proven track record owning PDN architecture for high-power SoCs/ASICs (AI accelerators, GPUs, or comparable compute silicon) at a product-line level
• Expert-level proficiency with SI/PI EDA tools: Ansys HFSS/SIwave, Cadence Sigrity/Clarity, Keysight ADS, or similar, including tool selection and methodology development
• Extensive hands-on lab validation experience - VNA, TDR, high-bandwidth oscilloscopes - and experience owning escalation-level debug
• Expertise in PCB stack-up design, transmission line theory, S-parameters, and channel modeling.
• Strong working knowledge of industry compliance standards (PCIe-SIG, USB-IF, MIPI Alliance)
• Demonstrated ability to set technical direction and standards across a hardware organization, and to mentor senior/staff-level engineers
• Good cross-functional leadership skills - comfortable driving alignment across ASIC, package, hardware, layout, and firmware teams at a strategic level
• Knowledge of ASIC characterization, PCB manufacturing, assembly, test, quality reliability is a plus.

Personal Attributes

• Demonstrates a proactive, solutions-oriented mindset and takes ownership of outcomes
• Collaborates effectively across cross-functional teams and fosters a strong team culture
• Intellectually curious, with a creative approach to problem-solving and technical challenges
• Execution-focused and results-driven, with a track record of delivering under ambiguity
• Self-motivated and highly accountable, with the ability to think strategically and drive long-term impact
• Strong verbal and written communication skills, with the ability to convey complex technical concepts clearly to diverse audiences.