Signal Integrity & Power Integrity (SI/PI) Engineer

L&T Technology Services; Bengaluru; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

L&T Technology Services in Bengaluru is seeking a qualified Signal Integrity & Power Integrity (SI/PI) Engineer with 4-10 years of experience to drive board-level SI/PI analysis and optimization for automotive and embedded computing platforms. The role requires strong expertise in high-speed interfaces, PDN analysis, and SI/PI validation using industry-standard tools such as Ansys HFSS.

You will collaborate with hardware, PCB layout, and validation teams to deliver reliable designs.

Qualifications

• 4-10 years of SI/PI experience.
• Expertise in PDN analysis and eye-diagram evaluation.
• Strong knowledge of high-speed interfaces and timing.
• Familiar with SI/PI validation using industry tools.

Responsibilities

• Perform channel modeling, extraction, and eye diagram analysis for high-speed interfaces.
• Conduct pre-layout and post-layout SI simulations to ensure compliance with interface standards.
• Analyze signal quality parameters including crosstalk, reflections, jitter, insertion loss, return loss, and TDR.
• Model, analyze, and optimize Power Distribution Networks (PDN).
• Perform AC/DC droop analysis, target impedance profiling, and power delivery optimization for ASICs, SoCs, and FPGAs.
• Collaborate with Hardware, PCB Layout (ECAD), and Validation teams to improve SI/PI performance.
• Develop SI/PI design guidelines and recommendations for board-level designs.
• Generate technical reports and provide design improvement recommendations based on simulation outcomes.

Skills

Signal Integrity

Power Integrity

High-Speed Interfaces

PDN Analysis

Eye Diagram Analysis

Education

Electronics/VLSI

Tools

Ansys HFSS

Job description

Job Description – Signal Integrity & Power Integrity (SI/PI) Engineer

Experience: 4-10 Years

Job Summary

We are looking for a highly skilled Signal Integrity & Power Integrity (SI/PI) Engineer to drive board-level SI/PI analysis and optimization for high-speed automotive and embedded computing platforms. The ideal candidate should possess strong expertise in high-speed interface design, simulation, PDN analysis, and SI/PI validation using industry-standard tools.

Key Responsibilities

• Perform channel modeling, extraction, and eye diagram analysis for high-speed interfaces.
• Conduct pre-layout and post-layout SI simulations to ensure compliance with interface standards.
• Analyze signal quality parameters including crosstalk, reflections, jitter, insertion loss, return loss, and TDR.
• Model, analyze, and optimize Power Distribution Networks (PDN).
• Perform AC/DC droop analysis, target impedance profiling, and power delivery optimization for ASICs, SoCs, and FPGAs.
• Collaborate with Hardware, PCB Layout (ECAD), and Validation teams to improve SI/PI performance.
• Develop SI/PI design guidelines and recommendations for board-level designs.
• Generate technical reports and provide design improvement recommendations based on simulation outcomes.

Required Skills

• Strong understanding of Signal Integrity and Power Integrity fundamentals.
• Experience with high-speed serial and memory interfaces.
• Hands-on expertise with:
• Ansys HFSS
• Experience in board-level timing analysis and simulation methodologies.
• Strong analytical, troubleshooting, and technical documentation skills.

Interface & Protocol Experience

• LPDDR4 / LPDDR5
• GMSL
• FPD-Link
• MIPI CSI
• USB
• Ethernet
• JEDEC-based memory interfaces

Preferred Skills

• Experience supporting automotive electronic platforms.
• Exposure to SI/PI challenges in high-current, high-speed computing systems.
• Knowledge of PCB stack-up optimization and electromagnetic behavior of high-speed designs.

Educational Qualification

• B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, Embedded Systems, VLSI, or related disciplines.