Senior Verification Engineer

AST SpaceMobile; Bengaluru; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

AST SpaceMobile is seeking a Senior FPGA Verification Engineer based in Bengaluru, India. The role involves designing and executing verification strategies for complex FPGA designs, requiring 4-8 years of experience in functional verification along with expertise in SystemVerilog and UVM.

Responsibilities include maintaining verification environments, performing simulation-based verification, and mentoring junior engineers. Join us in our mission to bring broadband to billions who remain unconnected.

Qualifications

• 4–8 years of hands-on experience in functional verification.
• Familiarity with high-speed interfaces like AXI, AXI-Stream, DDR, SPI.
• Experience with hardware/software co-verification is a plus.

Responsibilities

• Develop and maintain verification environments for FPGA designs.
• Create and execute verification plans and test scenarios.
• Drive debug and root-cause analysis of functional issues.

Skills

SystemVerilog

UVM

FPGA verification

Debugging skills

Cross-functional collaboration

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field

Tools

Cadence Xcelium

Xilinx Vivado

Pyhton

Tcl

Shell

Git

Job description

AST SpaceMobile is building the first and only global cellular broadband network in space to operate directly with standard, unmodified mobile devices based on our extensive IP and patent portfolio and designed for both commercial and government applications. Our engineers and space scientists are on a mission to eliminate the connectivity gaps faced by today’s five billion mobile subscribers and finally bring broadband to the billions who remain unconnected.

Position Overview

We are seeking a Senior FPGA Verification Engineer with 4–8 years of experience to design, develop, and execute comprehensive verification strategies for complex FPGA designs. This role requires strong hands‑on expertise in SystemVerilog and UVM, testbench architecture, and cross‑functional collaboration with design and system teams.

Key Responsibilities

• Develop and maintain SystemVerilog/UVM-based verification environments for FPGA block-level and top-level designs
• Create and execute verification plans, directed and constrained‑random test scenarios, assertions, and functional coverage
• Perform simulation‑based verification of FPGA designs using industry‑standard simulators
• Drive debug and root‑cause analysis of functional issues and work closely with FPGA RTL designers
• Integrate and maintain VIPs, scoreboards, checkers, and reference models
• Support FPGA bring‑up, validation, and debug activities on FPGA platforms and evaluation boards
• Review FPGA RTL, verification code, and test plans to ensure quality and completeness
• Mentor junior engineers and contribute to FPGA verification best practices
• Support regression runs, coverage closure, and release signoff

Qualifications

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field

Experience

4–8 years of hands‑on experience in functional verification

Preferred Qualifications

• Familiarity with cadence tools like Xcelium
• Familiarity with Xilinx Vivado
• Experience with hardware/software co‑verification
• Knowledge of high‑speed interfaces (AXI, AXI‑Stream, DDR, SPI)

Soft Skills

• Strong analytical and debugging skills
• Ability to work effectively in cross‑functional teams
• Excellent written and verbal communication skills
• Self‑driven with the ability to own verification tasks end‑to‑end
• High attention to detail and commitment to quality

Technology Stack

• Languages: SystemVerilog, Verilog, VHDL (working knowledge)
• Verification Methodology: UVM
• Simulation Tools: Xcelium, Questa, VCS
• FPGA Tools: Xilinx Vivado
• Debug Tools: SimVision
• Scripting: Python, Tcl, Shell
• Version Control: Git

Physical Requirements

• Ability to work in a standard office environment
• Ability to use a computer for extended periods
• Occasional lab work for FPGA bring‑up and debug

This job description may not be inclusive to the duties and responsibilities listed. Additional tasks may be assigned to the employee from time to time or the scope of the job may change as needed by business demands.

AST SpaceMobile is an Equal Opportunity, at‑will Employer; employment is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.