Senior Technical Staff Engineer – Emulation

Jobtailor; Bengaluru; On-site; INR 4,500,000 - 7,000,000; Full time

Job summary

Jobtailor seeks a senior hardware emulation engineer in Bengaluru to architect Veloce RTL models and UVM‑acceleration for high‑speed IPs. You will integrate RTL with firmware on emulation systems, develop bring‑up and debug frameworks, and drive hardware‑software co‑validation across projects.

The role requires 10+ years in RTL design, FPGA methods, and HW/SW co‑verification, with strong Verilog/SystemVerilog/C/C++ skills and DSP knowledge.

Qualifications

• BSEE / MSEE or equivalent degree.
• 10+ years in hardware emulation, RTL design, FPGA methods, or HW/SW co‑verification.
• Proficiency with Veloce platforms, VirtuaLAB environments, UVM‑acceleration, SystemC‑DPI.
• Proficient in Verilog, SystemVerilog, C/C++, RTL synthesis concepts.
• Deep knowledge of PCIe, Ethernet, DDR3/4/5, AMBA AHB/APB, SERDES, USB.
• Strong DSP theory and embedded processors (e.g., ARM Cortex) desirable.
• Strong analytical, debugging, and cross‑functional collaboration skills.
• Excellent written and verbal communication for documentation and exec presentation.

Responsibilities

• Architect Veloce RTL models and UVM acceleration for high‑speed IPs.
• Build CAD flows, emulation models, and system‑level use cases.
• Integrate RTL with bare‑metal firmware on emulation platforms.
• Develop bring‑up frameworks and debug RTL/firmware issues.
• Provide technical feedback to multiple engineering teams to shape roadmaps.
• Support pre/post‑sales design discussions with customers and sales.

Skills

RTL design

Verilog

SystemVerilog

C/C++

UVM-acceleration

SystemC-DPI

DSP concepts

ARM Cortex

debugging

communication

Education

BSEE / MSEE or equivalent

Tools

Veloce platforms

VirtuaLAB

Job description

Responsibilities

• Architect Veloce RTL models and UVM-acceleration for EdgeAI, PCIe, Ethernet, DDRC, etc.
• Build CAD execution flows, develop high‑fidelity emulation models, Veloce XACTORs, and system‑level use cases to drive deep performance and architectural validation on emulation platforms.
• Engineer shift‑left, end‑to‑end solution development by integrating hard and soft IP RTL with bare‑metal firmware on emulation systems.
• Develop system bring‑up frameworks, debug complex RTL/firmware issues, and accelerate time‑to‑market through comprehensive hardware‑software co‑validation.
• Provide technical feedback to Silicon Engineering, Software Engineering, and Marketing to enhance future product roadmaps.
• Provide expert pre‑ and post‑sales design support to customers and sales forces.

Requirements

• BSEE / MSEE or equivalent technical degree
• A minimum of 10+ years of progressive experience in hardware emulation, RTL design, FPGA methodologies, or HW/SW co‑verification
• Strong proficiency with Veloce platforms, VirtuaLAB environments, UVM‑acceleration, and SystemC‑DPI testing methodologies
• Proficient in Verilog, System Verilog, C/C++, RTL synthesis concepts
• Deep understanding of high‑speed IPs including PCIe, Ethernet, DDR3/4/5/, AMBA AHB/APB, SERDES, and USB
• Strong foundation in DSP theory/processor architectures and embedded processors (e.g., ARM Cortex platforms) is highly desirable
• Strong analytical and problem‑solving skills with a proven ability to debug complex, full‑stack hardware‑software issues and drive them to closure
• Excellent written and verbal communication skills for authoring documentation, training modules, and presenting to executive customers

Core Competencies

Demonstrates expertise in architecting Veloce RTL models and UVM‑acceleration for high‑speed IPs, integrating hardware and software components, and providing technical support throughout the product lifecycle. Proficient in debugging complex hardware‑software issues and enhancing product roadmaps through collaboration with engineering teams.