Senior Technical Architect - DFT

HCL Technologies Limited; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

HCLTech in Bengaluru seeks a principal DFT architect with 8–12 years of hands-on experience in DFT, including scan insertion, EDT, LBIST, ATPG coverage and pattern generation/simulation.

MBIST insertion/verification, DFT diagnostics, and repairability concepts are essential. Must guide a 4–6 member team, drive milestones under pressure, and communicate across sites. Exposure to ATE interfaces and post-silicon debug is valuable.

Qualifications

• B.Tech / M.Tech in a relevant engineering stream.
• 8–12 years of experience in DFT
• Hands-on expertise in scan insertion, EDT, LBIST, ATPG and pattern generation/simulation.

Responsibilities

• Define long-term DFT strategies and roadmaps for the organization.
• Spearhead R&D initiatives to improve test efficiency and fault coverage.
• Collaborate with foundries and EDA vendors to align on testing requirements.
• Provide technical mentorship and shape the DFT vision of the organization.

Skills

Visionary Leadership

Fault Models

Power-Aware DFT

Cross-Functional Leadership

Education

B.Tech / M.Tech

Tools

JTAG

iJTAG

PDL

Test Interfaces

Job description

B.Tech / M.Tech with 8 to 12 years of experience exclusively inDFT.

Sub-system / SOC level: Hands-on experience to do scan insertion, EDT, LBIST, ATPG coverage improvement, Pattern Generation/Simulation. Should have expertise on Simulation debug No-timing/Timing.
Exposure to SSN insertion is plus.

Sub-system / SOC level: Hands-on Experience to do MBIST Insertion, Verification, Pattern generation. Thorough with Diagnostics and Repairability concepts.
Good to have functional & integration knowledge of TAP controllers and JTAG. Working knowledge of JTAG, iJTAG, ICL, PDL etc.

Intel and AMD DFX insertion and val at SS and Top level.
QC checks post RTL insertion, SpyGlass, CDC, RDC, VCLP etc.

Should be able to handle team of 4-6 members. Drive team towards meeting Milestone in high pressure situation.

Good to have functional & integration knowledge of TAP controllers and JTAG

Must be aware of interface to ATEs, tester hand-off languages/TDL/Verilogand must know to drive/modify test procedures. Desirable to have experience in Post Silicon Debug on Tester.

Should either have hands-on or strong co-working experience with other dependent functions, Constraints development, STA & Physical Design. It is highly desirable that candidate should be able to come up with an implementation plan independently given a test plan.

Good at Communication. Conversant with Multi-site working culture. Able to guide team remotely.

Have done Technical front ending with client earlier.

Key Responsibilities

• 1. Define Long-Term Dft Strategies And Roadmaps For The Organization.
• 2. Spearhead R&D Initiatives To Improve Test Efficiency And Fault Coverage.
• 3. Collaborate With Foundries And Eda Vendors To Align On Testing Requirements.
• 4. Provide Technical Mentorship And Shape The OrganizationâÂÂS Dft Vision.

Skill Requirements

• 1. Visionary Leadership In Dft Technology And Its Integration With Broader Design Flows.
• 2. -Proficiency In Advanced Fault Models, Power-Aware Dft, And Emerging Standards.
• 3. -Strong Influence In Industry Forums And Collaborations With Eda Vendors.
• 4. -Expertise In Managing Complex Cross-Functional And Multi-Site Teams.

Other Requirements

1. Relevant Certifications Such As Certified Software Architect (Csa) Or Togaf (The Open Group Architecture Framework) Are Optional But Valuable.

HCLTech is a global technology company, home to more than 223,000 people across 60 countries, delivering industry‑leading capabilities centered on digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending June 2026totaled $14.8billion.