Senior Staff Physical Design Engineer

Mulya Technologies; Bengaluru; On-site; INR 4,000,000 - 8,000,000; Full time

Job summary

EnCharge AI in Bengaluru seeks a Senior Staff Physical Design Engineer with deep chip-level implementation expertise. You will drive physical design flows, ensure timing closure, and optimize for low power across complex designs for edge-to-cloud AI hardware.

The role requires 10–14 years in physical design, hands-on Cadence tool experience, and strong scripting skills (TCL/Python) for automation. On-site in Bengaluru with collaboration across design and foundry teams.

Qualifications

• 10-14 years of experience in physical design.
• Hands-on Cadence implementation experience is required.
• Strong knowledge of timing concepts and timing closure techniques.
• Experience with top-level and block-level physical design, hierarchical floorplanning is a plus.
• Proficiency in low-power design concepts and debugging.
• Experience with EM/IR checks, power grid verification, and issue resolution.
• Strong TCL or Python scripting for automation.

Skills

Cadence tools

Timing closure

Low-power design

Scripting (TCL/Python)

EM/IR checks

Physical design flow

Floorplanning

Tools

Cadence tools

Job description

Title: Senior Staff Physical Design Engineer

About Company:

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

About the Role

We are seeking a highly experienced Senior Staff Physical Design Engineer with a strong background in chip-level implementation and EDA tools. The ideal candidate will have deep expertise in physical design, timing closure, and low-power design.

Qualifications

• 10-14 years of experience in physical design (excluding other areas such as logic design or CAD).
• Strong understanding of EDA implementation for chip design, with hands-on experience in Cadence tools (must-have).
• Strong knowledge of timing concepts and timing closure techniques for chip design.
• Experience with both top-level and block-level physical design is required; experience with hierarchical floorplanning is a plus.
• Proficiency in low-power design concepts and debugging is necessary.
• Experience with EM/IR checks, debugging, and issue resolution, including power grid verification, is required.
• Strong scripting skills in TCL or Python for automation are important.
• Understanding of process concepts is needed for physical verification as part of routing tasks.
• Experience with physical design methodology and flow setup is preferred; this role will involve advanced flow evaluations.
• Additional experience in areas such as PDK management or foundry tapeout processes is a plus