Senior SOC Design Engineer - Networking Group

NVIDIA Corporation; Bengaluru; On-site; INR 2,400,000 - 4,200,000; Full time

Job summary

NVIDIA Corporation in Bengaluru invites an expert SOC Design and Integration Engineer to join our Networking chip design group. You will define milestones, develop system-level methodologies, and drive cross-functional teams toward SOC milestone execution.

The role requires hands-on experience with SOC development phases (architecture, RTL, verification, timing, physical design), exposure to Verilog/SystemVerilog and CAD tools, and a track record of tape-outs in high-volume SoCs.

Qualifications

• BS or MS with 3+ years of semiconductor design and architecture experience.
• Experience across ASIC development phases: architecture, micro-architecture, RTL, verification, timing, and physical design.
• Proficiency with Verilog/SystemVerilog and standard EDA tools; scripting in Python or similar is desirable.

Responsibilities

• Define project milestones from internal roadmaps and drive them through agile processes.
• Integrate all subsystems to deliver SOC milestones for verification at cluster, sub-system, SOC, and emulation levels.
• Collaborate with SOC Assembly and cross-functional teams to ensure smooth HW/SW interfaces and tape-outs.

Skills

SOC design

RTL design

Verilog / SystemVerilog

ASIC tape-out

Python scripting

C/C++

HW/SW interface

Physical design

DFT

Cross-functional collaboration

Education

BS or MS in Electrical Engineering/CS

Tools

Cadence

Indago

GDB

Verilog simulators

Job description

We are currently seeking an expert SOC Design and Integration Engineers with strong design fundamentals to work in Networking chip design group. You'll join a group of hardworking engineers to craft and implement the next generation innovative DPUs and Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing best high-speed communication devices, delivering the highest efficiency and lowest latency! The Networking Chip Design team in India is a new team which is growing at a fast pace.

What you'll be doing:

You are encouraged to understand all features of a given project and define project milestones based on internal roadmaps, assign them and track them through agile framework Define and develop system-level methodologies, tools, and IPs to build subsytems in an efficient and scalable manner. Work with SOC Assembly team and drive cross-functional teams towards SOC milestone execution. Be responsible for integrating all the pieces for a given defined project milestone and deliver the model to relevant teams for further verification at cluster/sub-system/SOC/emulation levels.

What we need to see:

• BS (or equivalent experience) / MS with 3+ years of practical semiconductor design and architecture experience building complex SoC’s.
• Must have firsthand experience & solid understanding of all phases of SOC development in multiple ASIC projects including ASIC architecture, Micro-Architecture, RTL design, verification, timing closure & Physical design.
• Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).
• C/C++ programming or python or any other industry-standard scripting language experience desirable.
• Experience working with software teams to tightly define the HW/SW interface including control/status registers, interrupt and error handling.
• Hands on experience in successful tape outs of multiple sophisticated, high-volume SoCs in advanced process nodes.
• Exposure to various Chip Design Functions to be able to collaborate and tackle sophisticated cross functional problems.
• Excellent verbal and written communication skills to interact with cross functional teams to build consensus.
• Experience in synthesis, physical design and DFT is a plus.
• Experience in RTL Build and Design Automation is a plus.

Ways to Stand out from the crowd:

• Chip lead type of technical leadership experience on delivering complex SOCs for enterprise and/or HPC applications.
• Experience in RTL coding and debug, as well as performance/power/area analysis and trade-offs Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area.
• Prior experience of smartNIC and/or high-speed interconnects.
• Strong coding skills in Perl, Python, or other industry-standard scripting languages.

Known throughout the technology industry as a top employer, NVIDIA delivers highly competitive salaries and a thorough benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/ NVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #LI-Hybrid NVIDIA pioneered accelerated computing. Today, our AI infrastructure powers global intelligence, transforming every industry. Learn more about NVIDIA.