Senior ASIC Engineer, Switch SoC

NVIDIA; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

NVIDIA's Networking Chip Design team in India seeks an expert SOC Design and Integration Engineer to help craft the next generation Switch Silicon chips. You will join a group of engineers to define milestones, develop scalable system-level methodologies, and drive SOC assembly across cross-functional teams.

The role requires hands-on experience across ASIC architecture, RTL, verification, timing closure, and physical design, plus scripting in Python or Perl.

Qualifications

• BS or MS with 4+ years in semiconductor design and SOC architecture.
• Experience across ASIC architecture, Micro-Architecture, RTL, verification, timing closure, and physical design.
• Experience with design and verification tools and scripting languages is desirable.

Responsibilities

• Understand project features, define milestones, and track progress in an agile framework.
• Develop system-level methodologies, tools, and IPs for SOCs in scalable ways.
• Lead SOC assembly and drive cross-functional teams toward milestone execution.
• Integrate components and hand off models for verification at cluster/sub-system/SOC levels.
• Proficient in Perl, Python, or other scripting languages.

Skills

C/C++

Python

RTL design

Verilog/SV

Communication

Teamwork

Education

BS or MS in Electrical Engineering/Computer Engineering

Tools

Cadence

Indago

GDB

Job description

We are currently seeking an expert SOC Design and Integration Engineer with strong design fundamentals to work in Switch Silicon group. You'll join a group of hardworking engineers to craft and implement the next generation innovative Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing best high-speed communication devices, delivering the highest throughput and lowest latency!

The Networking Chip Design team in India is a new team which is growing at a fast pace.

What you'll be doing:

• You are encouraged to understand all features of a given project and define project milestones based on internal roadmaps, assign them and track them through agile framework
• Define and develop system-level methodologies, tools, and IPs to build SOCs in an efficient and scalable manner.
• Work on SOC Assembly and drive cross-functional teams towards SOC milestone execution.
• Be responsible for integrating all the pieces for a given defined project milestone and deliver the model to relevant teams for further verification at cluster/sub-system/SOC/emulation levels.
• Have good grasp of Perl, Python, or other industry-standard scripting languages.

What we need to see:

• BS (or equivalent experience) / MS with 4+ years of practical semiconductor design and architecture experience building complex SoC’s.
• Must have firsthand experience & solid understanding of all phases of SOC development in multiple ASIC projects including ASIC architecture, Micro-Architecture, RTL design, verification, timing closure & Physical design.
• Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).
• C/C++ programming or python or any other industry-standard scripting language experience desirable.
• Experience working with software teams to tightly define the HW/SW interface including control/status registers, interrupt and error handling.
• Hands on experience in successful tape outs of multiple complex, high-volume SoCs in advanced process nodes.
• Exposure to various Chip Design Functions to be able to collaborate and solve complex cross functional problems.
• Excellent verbal and written communication skills to interact with cross functional teams to build consensus.
• Good teamwork spirit and collaboration skills with team members.
• Experience in synthesis, physical design and DFT is a plus.
• Background in RTL Build and Design Automation is a plus.

Ways to stand out from the crowd:

• Chip lead type of technical leadership experience on delivering complex SOCs for enterprise and/or HPC applications.
• Experience in RTL coding and debug, as well as performance/power/area analysis and trade-offs
• Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area.
• Strong coding skills in Perl, Python, or other industry-standard scripting languages.

Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.