ASIC Design Engineer - Performance Monitoring

NVIDIA Corporation; Bengaluru; Hybrid; INR 1,800,000 - 2,800,000; Full time

Job summary

NVIDIA in Bengaluru is seeking an ASIC Design Engineer to contribute to RTL design and SOC flows. Join a team that pushes the envelope in GPU/SOC technology andautomation to deliver high-quality IP.

You will work with architecture, verification, and software teams to implement, debug, and optimize RTL across the complete design cycle, while applying scripting to automate flows and improve productivity.

Qualifications

• B.Tech or M.Tech in Electronics or Computer Engineering.
• 3+ years of relevant industry experience.
• Experienced in RTL design (Verilog) and SOC design/implementation flows.
• Strong scripting skills in Perl and Python.

Responsibilities

• Define and develop system-level RTL and methodologies to measure performance on GPUs/SOCS.
• Design and implement RTL features across the SOC design cycle.
• Run and debug RTL checks to ensure design quality (CDC, RDC, Lint, Synthesis, Logic-Equivalence).
• Define, develop, and automate flows to build and support a system-level IP.
• Collaborate with Architects, Designers, Verification and SW engineers.

Skills

RTL design

SOC architecture

Perl/Python scripting

Education

B.Tech or M.Tech in Electronics/Computer Engineering

Tools

dc_shell

VCS

Debussy

GDB

Job description

NVIDIA System-On-Chip (SOC) group is hiring for an ASIC Design Engineer! The complexity of the chips we build has increased manifold over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand. We are looking for a top ASIC Design Engineer to join our team. In this role, you should have real passion for RTL design implementation and methodologies that enable high quality system-level IP design.

What youll be doing:

• Be an integral part of the team defining and developing system-level RTL and methodologies to measure performance on the industry's leading GPUs/SOCs.
• Design and implement RTL features - work through the entire design cycle for SOC.
• Run and debug RTL checks to ensure design quality (e.g. CDC, RDC, Lint, Synthesis, Logic-Equivalence and more)
• Define, develop, and automate flows and methodologies to efficiently build and support a system-level IP
• Work with architects, designers, verification and SW engineers to accomplish your tasks.

What we need to see:

• B.Tech or M.Tech in Electronics or Computer Engineering.
• 3+ years of relevant industry experience.
• Experienced in RTL design (Verilog), System-On-Chip design/implementation flows, and design automation.
• Good understanding of SOC/IP (u)architecture (e.g., data flow, control, multiple clock/power domains handling, latency analysis).
• Strong coding skills in Perl, Python or other industry-standard scripting languages.
• Excellent debugging and analytical skills.
• Exposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Debussy, GDB).
• Great communication and collaboration skills to interact within the team and with cross functional teams.
• Adept at using AI tools to enhance productivity and solve complicated problems

NVIDIA is widely considered one of the technology world’s most desirable employers. We employ some of the most forward-thinking and innovative people in the world. Are you passionate about joining our life’s work to amplify human imagination and intelligence? If you are creative, collaborative, and have real passion for design, methodology, and automation, we want to hear from you!

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