Senior Research and Development Engineer - Embedded Software and FPGA

Synopsys India Pvt Ltd; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Synopsys India Pvt Ltd in Bengaluru is seeking a Senior R&D Engineer skilled in C/C++, data structures, and FPGA-related algorithms to join the ProtoCompiler R&D team. You will design, optimize, and maintain large-scale software systems, collaborating with cross-functional teams to deliver high-performance silicon tooling.

You will apply your knowledge of RTL-level Verilog/VHDL, graph algorithms, and advanced data structures to improve partitioning and validation workflows, contributing to

Qualifications

• B.Tech/M.Tech in Computer Science or Electrical Engineering from a reputed institute.
• 2+ years of experience designing, developing, and maintaining large-scale EDA or system software solutions.
• Strong programming skills in C and C++ across Windows and Unix platforms.
• Solid understanding of data structures, graph algorithms, and software optimization techniques.
• Familiarity with digital logic design, Verilog/VHDL at RTL level, and logic optimization concepts.
• Experience with FPGA design tools and flows is a plus.

Responsibilities

• Designing, developing, troubleshooting, debugging, and maintaining large-scale, efficient software systems for the HAPS ProtoCompiler partition flow.
• Implementing and optimizing advanced data structures and algorithms in C/C++ to meet challenging performance and scalability requirements.
• Collaborating with product validation (PV) teams to plan, execute, and automate comprehensive testing strategies.
• Working on logic optimization, clock inference, and marking, as well as preparing designs for partitioning and estimating area and other critical design metrics.
• Maintaining and supporting existing features and products, ensuring robustness and quality across releases.
• Engaging with digital logic design, and applying your knowledge of Verilog/VHDL at the RTL level to enhance hardware/software co-design workflows.

Skills

C/C++

Data structures

Graph algorithms

Verilog/VHDL

FPGA design tools

Education

B.Tech/M.Tech in Computer Science or Electrical Engineering

Tools

FPGA design tools

Job description

Job Title

R&D Engineer, Sr Engineer (C/C++, Data structures, Algorithm, FPGA)

General Information

• Job Title R&D Engineer, Sr Engineer (C/C++, Data structures, Algorithm, FPGA)
• Job ID 15488
• Country India
• City Bengaluru
• Date Posted 26-Feb-2026
• Job Category Engineering
• Job Subcategory R&D Engineering
• Hire Type Employee
• Remote Eligible No

Descriptions & Requirements

Job Description and Requirements

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are: You are a passionate and driven engineering professional with a deep curiosity about how things work and a relentless desire to solve complex problems. You thrive in a collaborative environment, working alongside talented peers to deliver robust, high-performance solutions that make a tangible impact. You bring a strong foundation in computer science or electrical engineering, coupled with hands-on experience in developing and maintaining large-scale EDA software. Your expertise in C/C++, data structures, and graph algorithms is complemented by your understanding of digital logic design and hardware description languages. You are proactive, detail-oriented, and eager to continuously learn new technologies and methodologies. Whether you’re designing innovative algorithms or troubleshooting intricate system issues, you approach every challenge with analytical rigor and creativity. You are committed to quality, enjoy working with cross-functional teams, and are motivated by the opportunity to influence the future of chip design and prototyping. If you value diversity, inclusion, and believe in the power of technology to change the world, Synopsys is the place where your ambitions can thrive.

What You’ll Be Doing:

• Designing, developing, troubleshooting, debugging, and maintaining large-scale, efficient software systems for the HAPS® ProtoCompiler partition flow.
• Implementing and optimizing advanced data structures and algorithms in C/C++ to meet challenging performance and scalability requirements.
• Collaborating with product validation (PV) teams to plan, execute, and automate comprehensive testing strategies.
• Working on logic optimization, clock inference, and marking, as well as preparing designs for partitioning and estimating area and other critical design metrics.
• Maintaining and supporting existing features and products, ensuring robustness and quality across releases.
• Engaging with digital logic design, and applying your knowledge of Verilog/VHDL at the RTL level to enhance hardware/software co-design workflows.
• Participating in code reviews, design discussions, and knowledge-sharing sessions within the team and broader engineering organization.

The Impact You Will Have:

• Accelerate time-to-market for cutting-edge silicon designs by enabling early embedded software development and hardware/software co-design.
• Help customers avoid costly device re-spins through robust prototyping solutions that support rapid iteration and validation.
• Drive improvements in software quality, performance, and reliability for ProtoCompiler and HAPS solutions.
• Support the creation of innovative verification and validation methodologies for processor subsystems and full SoC designs.
• Contribute to the evolution of Synopsys’ industry-leading EDA tools, shaping future product capabilities and features.
• Empower teams across the globe to build high-performance, energy-efficient chips for applications ranging from AI and automotive to IoT and beyond.

What You’ll Need:

• B.Tech/M.Tech in Computer Science or Electrical Engineering from a reputed institute.
• 2+ years of experience designing, developing, and maintaining large-scale EDA or system software solutions.
• Strong programming skills in C and C++ across Windows and Unix platforms.
• Solid understanding of data structures, graph algorithms, and software optimization techniques.
• Familiarity with digital logic design, Verilog/VHDL at RTL level, and logic optimization concepts.
• Experience with FPGA design tools and flows is a plus.

Who You Are:

• Innovative thinker with a passion for technology and problem-solving.
• Effective communicator, comfortable working in cross-functional and global teams.
• Analytical, detail-oriented, and committed to delivering high-quality results.
• Adaptable and open to learning new tools, methodologies, and technologies.
• Collaborative team player who values diversity and inclusion.
• Resilient, proactive, and able to thrive in a fast-paced, dynamic environment.

The Team You’ll Be A Part Of

You will join the ProtoCompiler R&D team in Bangalore, a group of talented engineers dedicated to developing world-class partitioning flows for the Synopsys HAPS® Prototyping Solution. Our team thrives on innovation, collaboration, and technical excellence, working closely with global engineering, validation, and product management groups to deliver industry-leading tools that power the next generation of silicon design.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Experience Level Senior Level