Senior Principal Analog Design Lead

NXP Semiconductors NV; Pune District; On-site; INR 3,800,000 - 7,000,000; Full time

Job summary

NXP Semiconductors NV in Pune, India, seeks an experienced Senior Analog IP Architect to define SOC analog architectures and lead the IP development for MCU products. You will own specifications, oversee design implementation, verification, layout, and validation, and mentor junior engineers within the analog team.

You will drive coordination with global R&D methods, ensure quality integration, and provide documentation for design reviews and reliability.

Qualifications

• Bachelor's degree in electronic/electrical engineering required; Master's degree preferred.
• 15+ years of IC-design industry experience.
• Experience with IP areas: ADC, DAC, PLL, oscillators, references, LDO, DC-DC, PGA, amplifiers, filters.
• Experience creating/using behavioral models (AMS, DMS, Matlab, System-C or equivalent) is a plus.
• Strong communication and teamwork skills are required.
• Mentoring and development of junior engineers.

Responsibilities

• Define SOC analog architecture and IP-level specs for MCU designs.
• Oversee implementation, simulation, layout, and validation of mixed-signal IP.
• Lead analog team and coordinate with R&D design methodology.
• Provide design documentation for reviews, integration requirements, and reliability.
• Ensure post tape-out support: characterization, production test, life testing, debugging.
• Collaborate with SOC teams for quality integration of analog IP/modules.

Skills

Strong communication

Teamwork

Mentoring

Junior engineers coaching

Education

Bachelor's degree in electronic/electrical engineering

Master's degree preferred

Job description

Role Summary:

• Define SoC analog architecture and IP requirements starting from system level specifications.
• Drive circuit architectures definition and best-in-class design implementation capable of meeting R&D targets in terms of innovation, performance and reliability.
• Create and ensure robust and high-quality IP from requirements.
• Project leading and manager of the analog team assigned to the project.
• Ownership for the implementation, simulation, layout, and validation of mixed signal IP for microcontrollers (MCUs). This IP could be data converters (ADC, DAC), clock generators (crystal oscillators, free running oscillators, PLL) or any other miscellaneous analog or mixed signal IP that adds value to NXP MCUs products, in line with R&D design methodology.
• Local or remote co-working with the other project leader during SOC design execution.
• Provide technical documentation required for design reviews, SOC integration, industrialization and reliability.

Your Responsibility:

• Define SOC analog architecture and IP-level specifications related to microcontroller products (MCU) new design with the target of quality and industrialization.
• Verify expected performances are met using simulation (behavioral, transistor level or combinations) and they are matching silicon performances.
• Drive analog team during new SOC development and alignment with R&D global design methodology.
• Co-operation with SOC teams on quality integration of the analog IP/modules within new SOC products.
• Provide documentation of the design, design reviews, and integration requirements of IP and sub-systems.
• Guarantee post tape-out support - characterization, production test, life testing, debug.

Your Profile:

• Bachelor's degree in electronic/electrical engineering required, Master's degree is preferred.
• 15+ years of product development with IC-design Company experience.
• Experience with one or more of these IP areas: ADC, DAC, PLL, oscillators, Voltage and current references, LDO, DC-DC, PGA, amplifiers, filters, etc...
• Experience creating and using behavioral models is a plus (AMS, DMS, Matlab, System-C or equivalent).
• Strong communication and teamwork skills are required.
• Mentoring and development of junior engineers.