Senior NVM Design Engineer

Connectpro Management Consultants; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Connectpro Management Consultants in Bengaluru, India seeks a Senior NVM Design Engineer with 12+ years to lead architecture, design, and delivery of OTP and EEPROM memory IPs, from concept through silicon qualification.

The role requires deep technical depth, cross-functional leadership, and ownership of NVM IPs from design to production release across multiple technologies. Competitive compensation and mentorship opportunities exist.

Qualifications

• 12+ years of hands-on OTP/EEPROM memory design experience.
• Strong expertise in NVM bit-cell and peripheral circuits.
• Experience across multiple process nodes and foundry tech.
• Proficiency with SPICE, corner analysis, and statistical modeling.
• Leadership across IP development and silicon bring-up.

Responsibilities

• Lead architecture and circuit design of OTP and EEPROM memory IPs.
• Define programming algorithms, redundancy schemes, reliability mechanisms, and safety features.
• Drive PPA optimization across multiple technology nodes.
• Own top-level NVM IP micro-architecture and interfaces to controllers.
• Oversee silicon bring-up, debug, and qualification strategies.
• Mentor junior designers and contribute to roadmaps.

Skills

NVM bit-cell design

High-voltage design

Programming/erase algorithms

Silicon debug

SPICE & corner analysis

Process node expertise

Education

Electrical Engineering degree

Job description

Job Role: Memory Design

Req Title: Senior NVM Design Engineer

Experience: 12-15 Years

We are seeking a Senior NVM Design Engineer with 12+ years of industry experience in OTP and/or EEPROM memory design to lead the architecture, design, and delivery of high-quality non-volatile memory IPs. This role requires deep technical expertise, strong cross-functional leadership, and ownership of NVM IPs from concept through silicon qualification and production release.

Architecture & Design

• Lead architecture definition and circuit design of OTP and EEPROM memory IPs, including bit-cell, periphery, high-voltage devices, charge pumps, sense amplifiers, and write/erase control.
• Define programming algorithms, redundancy schemes, reliability mechanisms, and safety features.
• Drive PPA (Power, Performance, Area) optimization across multiple technology nodes.
• Own top-level NVM IP micro-architecture, including interfaces to digital controllers and test logic.

Responsibilities for Internal Candidates

Implementation & Silicon Execution

• Oversee schematic design, simulation, and verification (functional, corner, Monte-Carlo, aging).
• Partner closely with layout teams to ensure DRC/LVS clean, robust HV-aware layouts with strong EM/IR and reliability margins.
• Support DFT, BIST, IJTAG, and test-mode implementation, including fuse evaluation and trimming flows.
• Drive silicon bring-up, debug, and characterization, including programming window optimization and yield learning.
• Define and support qualification strategies (HTOL, bake, cycling, retention, endurance).
• Work with Quality & Reliability teams to ensure product readiness and cost-effective qualification.
• Own failure analysis and root-cause resolution for NVM-related issues.

Cross-Functional Leadership

• Act as technical lead interfacing with Technology Development, Digital Design, Validation, Product, and Foundry partners.
• Mentor junior and mid-level designers; establish best practices and design methodology for NVM IP.
• Contribute to multi-generation NVM roadmaps and technology scaling strategies.

Qualifications for Internal Candidates

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering or related field.
• 12+ years of hands-on experience in OTP and/or EEPROM memory design.
• Strong expertise in:
• NVM bit-cell and peripheral circuit design
• High-voltage devices and reliability-aware design
• Programming/erase algorithms and margin analysis
• Silicon debug and characterization
• Proficiency with SPICE simulation, corner analysis, and statistical modeling.
• Experience working across multiple process nodes and foundry technologies.

Preferred Qualifications

• Experience with both OTP and EEPROM (cell-based or fuse-based implementations).
• Familiarity with automotive or safety-critical requirements (AEC-Q100, ISO-26262).
• Exposure to NVM controllers, digital interfaces, and test vehicles.
• Prior experience leading IP tape-outs and production releases.
• Strong documentation and technical review skills.