Senior Logic Design Engineer

Headway Consultant Pune; Mhalunge; Sur place; INR 900 000 - 1 300 000; Plein temps

Avantages offerts par ce poste

Résumé du poste

Headway Consultant Pune is seeking a Staff Logic Engineer to architect, implement, and deliver complex FPGA-based logic for high-speed protocol analysis and test systems. The role combines hands-on RTL development, transceiver and interface integration, verification, lab debug, and technical leadership across PCI Express (PCIe), Compute Express Link (CXL), Ethernet, and USB solutions.

You will work hands-on with RTL in SystemVerilog/Verilog/VHDL, integrate PCIe, CXL, Ethernet, and USB

Qualifications

• Experience with at least two high-speed protocol families among PCIe, CXL, Ethernet, and USB.
• Bachelor's or Master's in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field.
• 8+ years of digital design with hands-on FPGA development.
• Proficient in SystemVerilog/Verilog/VHDL including FSMs, pipelining, and data-paths.
• Strong debugging, timing closure, and on-chip debug across large FPGAs.
• Experience with DDR4/DDR5, DMA, AXI, Avalon or similar buses.
• Excellent written and verbal communication; able to work from Pune site.

Responsabilités

• Architect, implement, and deliver complex FPGA-based logic for high-speed protocol analysis and test systems.
• Own RTL design, clocking, data paths, and interfacing across PCIe, CXL, Ethernet, and USB.
• Develop tests, verification plans, and testbenches; use SystemVerilog/UVM.
• Support lab bring-up, debugging, and issue triage.

Connaissances

FPGA design

RTL design

SystemVerilog

Verilog

VHDL

Timing closure

Debug & lab verification

Cross-functional collaboration

Formation

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related discipline

Outils

AMD Xilinx UltraScale+/Versal

Intel Stratix/Agilex

Vivado

SignalTap

Description du poste

Profile - Sr. Logic Designer | FPGA & High-Speed Protocol Interfaces

Location - Hinjewadi, Pune

Working Days - 5 days

Qualification - BSCS, BSCE, or BSEE degree.

Client Brief - A 61 years old US product based MNC.

Role Summary

We are seeking a Staff Logic Engineer to architect, implement, and deliver complex FPGA-based logic for high-speed protocol analysis and test systems. The role combines hands-on RTL development, transceiver and interface integration, verification, lab debug, and technical leadership across PCI Express (PCIe), Compute Express Link (CXL), Ethernet, and USB solutions.

What You Will Do

FPGA Architecture and RTL Design

• Integrate and customize FPGA IP for PCIe, CXL, Ethernet, USB, DDR memory, DMA, and other high-speed interfaces.
• Own FPGA architecture and microarchitecture for protocol capture, packet processing, filtering, triggering, traffic generation, timestamping, and data movement.
• Design, implement, and maintain synthesizable RTL using SystemVerilog, Verilog, or VHDL for high-throughput, low-latency datapaths and control logic.
• Develop robust clocking, reset, clock-domain crossing, and data-path schemes across multiple clock domains and transceiver interfaces.
• Optimize designs for timing closure, resource utilization, power, latency, throughput, and design maintainability on large FPGAs.

High-Speed Protocol Interface Development

• Analyze protocol traces and lab measurements to identify interoperability, performance, and corner-case issues.
• Develop FPGA logic for complex protocol interfaces such as PCIe, CXL, Ethernet, and USB, including packet framing, flow control, error handling, link monitoring, and protocol-aware processing.
• Work with high-speed serial transceivers, reference clocks, equalization controls, link-training behavior, lane alignment, and multi-lane data paths.
• Partner with protocol, hardware, firmware, and software teams to translate specifications and product requirements into implementable FPGA features.

Verification, Implementation, and Lab Debug

• Create design specifications, verification plans, assertions, self-checking simulations, constrained-random tests, and reusable testbench components.
• Collaborate with verification engineers using SystemVerilog/UVM and coverage-driven methodologies; perform block-level and system-level verification.
• Execute synthesis, place-and-route, static timing analysis, CDC/RDC analysis, lint, and design-rule checks; resolve implementation and timing issues.
• Debug FPGA hardware using embedded logic analyzers such as Vivado ILA or SignalTap, protocol analyzers, oscilloscopes, and other lab equipment.
• Support board bring-up, system integration, regression testing, issue triage, root-cause analysis, and release readiness.

Technical Leadership and Collaboration

• Mentor engineers in FPGA design, timing closure, high-speed interfaces, protocol behavior, and disciplined problem solving.
• Communicate technical status, risks, tradeoffs, and recommended actions clearly to engineering and program leadership.
• Provide technical direction for complex features from concept through production release while remaining deeply hands-on in design and debug.
• Lead architecture and RTL reviews, establish coding and verification standards, and drive design quality, reuse, and documentation. Coordinate effectively with cross-functional and geographically distributed teams, including product management, systems engineering, PCB hardware, firmware, software, validation, manufacturing, and customer support.

Required Qualifications

• Demonstrated experience with at least two high-speed protocol families among PCIe, CXL, Ethernet, and USB, plus the ability to become effective across the remaining interfaces.
• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
• Typically 8+ years of relevant digital design experience, with substantial hands-on FPGA development and delivery of production-quality logic.
• Expertise in RTL design with SystemVerilog, Verilog, or VHDL, including synchronous design practices, finite-state machines, pipelining, arbitration, buffering, and error recovery.
• Strong knowledge of high-speed serial transceivers and FPGA implementation flows on AMD Xilinx UltraScale+/Versal or Intel Stratix/Agilex platforms.
• Proven experience with synthesis, constraints, static timing analysis, timing closure, CDC/RDC, reset architecture, and on-chip debug.
• Experience integrating external memory and high-bandwidth data movement, including DDR4/DDR5, DMA, AXI, Avalon, or comparable on-chip buses. Strong debugging and analytical skills across RTL simulation, FPGA implementation, board-level behavior, and protocol-level observations.
• Ability to create clear architecture documents, interface specifications, test plans, and engineering documentation.
• Effective written and verbal communication skills and the ability to work from the Pune engineering site in a collaborative product-development environment.

Preferred Qualifications

• Experience with Ethernet MAC/PCS/FEC datapaths, multi-rate designs, high-speed SerDes, or packet processing pipelines.
• Experience with USB 3.x/USB4 protocol logic, Type-C related system considerations, or USB protocol analysis and test.
• Background in protocol analyzers, traffic generators, exercisers, compliance tools, or other test and measurement products.
• Familiarity with formal verification, FPGA prototyping, hardware emulation, or advanced performance modeling.
• Experience working directly with customers or field teams to resolve complex interoperability and product issues.
• Deep knowledge of PCIe link and transaction layers, LTSSM behavior, equalization, error handling, and protocol analyzer concepts.
• Experience with CXL.io and familiarity with CXL.cache and CXL.mem concepts, coherency-related flows, or CXL compliance and interoperability challenges.
• Experience with Python, Tcl, C/C++, scripting, continuous integration, automated regression, and source-control workflows such as Git.

Success In the Role -

Deliver scalable FPGA architectures, clean RTL, predictable timing closure, and reliable protocol behavior across demanding high-speed interfaces. Raise engineering quality through strong reviews, mentoring, clear decisions, practical risk management, and effective cross-functional execution.