Senior Lead Engineer - SoC Design Verification

NXP Semiconductors; Pune District; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

NXP Semiconductors India is seeking a Senior Design Verification Engineer to lead RTL functional verification for automotive networking devices. You will architect, enhance, and maintain UVM‑based environments and drive metric‑driven verification from planning to closure.

The role involves developing testbenches with SystemVerilog, C, and UVM, defining verification strategies, and collaborating with Architecture, DV, Firmware, and Validation teams to meet stringent automotive quality standards.

Qualifications

• B.S./M.S. Electrical/Computer Engineering or similar.
• 8+ years of proven ASIC/SoC verification experience, taking chips from spec to tapeout.
• Expertise with UVM and/or SystemVerilog based verification.
• Experience in standard ASIC verification including test plan and testbench creation.
• Experience with directed and constrained random stimulus, and low power verification.
• Familiarity with UPF/CPF flows and SVA assertions.
• Proficiency in C/C++, Python scripting, and verification tooling.

Responsibilities

• Create robust verification architecture and plan; drive metric closure per NXP process.
• Develop UVM-based testbenches and C-based test cases for HW‑FW simulation.
• Define verification strategy for IP, Sub‑System and SoC verification (Directed, CR and Formal).
• Develop UVM components: agents, scoreboards, environments, sequences, and assertions.
• Ensure regression coverage and drive closure for functional and power‑aware verification.
• Collaborate with Architecture, DV, and Validation teams to ensure timely delivery of quality automotive solutions.

Skills

UVM

SystemVerilog

C/C++

Python

SVA

Low power verification

Directed/Constrained random

Testbench development

Education

B.S./M.S. Electrical/Computer Engineering

Tools

GIT

Jira

Confluence

Job description

We are seeking a highly driven Senior Design Verification Engineer for RTL functional verification of cutting‑edge in‑vehicle networking devices within NXP’s next‑generation automotive product line. In this individual‑contributor role, you will architect, enhance, and maintain advanced UVM‑based and C‑based verification environments. You will define robust verification strategies, craft comprehensive test plans, and drive metric‑driven verification to full closure. You will collaborate closely with world‑class teams across Design, Architecture, Validation, and Firmware, ensuring seamless integration and adherence to rigorous automotive design and quality processes. This is an opportunity to shape the verification strategy of high‑impact automotive solutions that define reliability, safety, and performance for vehicles worldwide.

Main Job Tasks and Responsibilities:

• Create robust verification architecture, verification testplan and verification metric closure documentation to comply with NXP verification and validation process.
• Architect and develop testbenches using System Verilog and UVM for functional and power aware RTL verification.
• Contribute to defining verification strategy (Directed, Constrained random and Formal) for IP, Sub‑System and SoC verification.
• Develop UVM components like Agents (active and passive), Scoreboards and Environment etc., Develop Assertions, functional coverage.
• Develop Test plan, UVM based test sequences, layered sequences, virtual sequencers.
• Drive closure of verification metrics to cover verification space.
• Work with a team to identify and close gaps in Functional, Power aware and Gate level timing Simulation.
• Develop ‘C’ testcases for HW‑FW Simulation and FPGA Prototyping.
• Regression setup, debug of RTL and Gate level Netlist.
• Work closely with Architecture, digital and analog design, DV and validation teams to ensure timely delivery of quality products.

Minimum Required Qualifications

• B.S./M.S. Electrical/Computer Engineering (or similar degrees)
• 8+ Years of proven track record of ASIC/SoC verification, taking several chips from specification to tape out.
• Proven Expertise with UVM and/or System Verilog based verification.
• Proven experience of standard ASIC verification including Planning Test Testbench creation.
• Code and Functional Coverage Directed and Constrained random stimulus generation and test.
• Low power verification.
• UPF/CPF Flow.
• SVA Assertion.
• C/C++, Perl, Python scripting.
• Experience working with tools like GIT, Jira, Confluence.

More information about NXP in India... #LI-2734 NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. For more information, visit www.nxp.com Bright Minds. Bright Futures. We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills.

Commitment At NXP. We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year‑on‑year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality.